Depletion-load NMOS logic: Difference between revisions

Content deleted Content added
Citation bot (talk | contribs)
m Removed URL that duplicated unique identifier. | You can use this bot yourself. Report bugs here.| Activated by User:Nemo bis | via #UCB_webform
Fixed link
Line 41:
 
===The HMOS processes===
In the early to mid-1980s, [[CMOS]] was still quite slow and used mostly for the [[4000 series]], [[Static RAM]]s, and low-power [[Application-specific integrated circuit|ASIC]]s (such as [[watch#display#digitalDigital|watch]] and [[calculator]] ICs). Advanced processes for depletion-load nMOS, such as Intel's family of scaled '''HMOS''' (''High density, short channel MOS'') processes were therefore used for most microprocessors, certain types of memories, and many support and peripheral ICs. The first nMOS process called HMOS (late 1976) was originally used for Intel's then central [[static RAM]] products. Although primarily intended for fast SRAM,<ref>''See http://lark.tu-sofia.bg/ntt/eusku/readings/art_1.pdf''.</ref> it was soon employed also for faster and/or less power hungry versions of the 8085, 8086, and other chips. HMOS was also licensed to other manufacturers, such as Motorola, which used it to manufacture the [[Motorola 68000]] series, for instance. According to Intel, HMOS-II (1979) provided twice the density and four times the speed/power product over other typical contemporary depletion-load nMOS processes.<ref>See for instance: ''Leo J.Scanlon The 68000 Principles and programming.''</ref> HMOS, HMOS II, HMOS III, and HMOS IV were together used for many different kinds of processors; the [[8085]], [[8048]], [[8051]], [[8086]], [[Intel 186|80186]], [[Intel 286|80286]], and many others, but also for several generations of the same basic design, see [[datasheet]]s.
 
===Further development===