FPGA prototyping: Difference between revisions

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Certus brings enhanced RTL-level visibility to FPGA-based debugging. It uses a highly efficient multi-stage concentrator as the basis for its observation network to reduce the number of LUTs required per signal to increase the number of signals that can be probed in a given space. The ability to view any combination of signals is unique to Certus and breaks through one of the most critical prototyping bottlenecks.<ref>{{cite web|url=http://www.tek.com/document/whitepaper/break-through-your-asic-prototyping-bottlenecks | title=Break Through Your ASIC Prototyping Bottlenecks| date= 2012-10-23|accessdate=2012-10-30}}</ref>

EXOSTIV uses large external storage and gigabit transceivers to extract deep traces from FPGA running at speed. The improvement lays in its ability to see large traces in time as a continuous stream or in bursts. This enables exploring extended debugging scenarios that can't be reached by traditional embedded instrumentation techniques. The solution claims saving both the FPGA I/O resources and the FPGA memory at the expense of gigabit transceivers, for an improvement of a factor of 100,000 and more on visibility.<ref>{{cite web|url=httphttps://www.exostivlabs.com/why-exostiv/ | title=Why EXOSTIV?| date= 2015-10-14|accessdate=2015-11-25}}</ref><ref>{{cite web|url=https://www.exostivlabs.com/asic-soc-prototyping/ | title=ASIC/SoC Prototyping| accessdate=2020-04-12}}</ref>

==See also==