Systolic array: Difference between revisions

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The name derives from analogy with the regular pumping of blood by the heart. In [[computer architecture]], a '''systolic array''' is an arrangement of [[data processing unit]]s ([[DPU]]s, almost similar to [[central processing unit]]s ([[CPU]])s, but without a [[Program counter]], since operation is transport-triggered, i. e. by the arrival of a data object, like known also from [[Transport Triggered Architectures]]), in an [[array]] (often rectangular) where data flows across the array between neighbours, usually with different data flowing in different directions. The [[Data stream]]s entering and leaving the ports of the array are generated by [[auto-sequencing memory]] units (ASMs). Each ASM includes a [[Data counter]]. In [[Embedded System]]s a data stream may also be inputted from and/or outputted to an external source.

The systolic array paradigm, data-stream-driven by data counters, is the counterpart of the [[von Neumann paradigm]], instruction-stream-driven by a program counter (also see [[von Neumann]] or [[von Neumann architecture]]). Because the systolic array paradigm includes multiple data counters, it supports [[data parallelism]].