Flash memory controller: Difference between revisions

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Flash memory can withstand a limited number of program-erase cycles. If a particular flash memory block were programmed and erased repeatedly without writing to any other blocks, the one block would wear out before all the other blocks thereby prematurely ending the life of the storage device. For this reason flash controllers use a technique called [[wear leveling]] to distribute writes as evenly as possible across all the flash blocks in the SSD. In a perfect scenario this would enable every block to be written to its maximum life so they all fail at the same time.<ref name="Li-Pin Chang">{{cite paper |citeseerx = 10.1.1.103.4903 |title=On Efficient Wear Leveling for Large Scale Flash Memory Storage Systems |author=Chang, Li-Pin |date=2007-03-11 |publisher=National ChiaoTung University, HsinChu, Taiwan }}</ref>

==Flash tratranslation layer (FTL) and mapping==

{{main|Flash file system}}

==nslation layer (FTL) and mapping==

Usually, flash memory controllers also include the "flash translation layer" (FTL), a layer below the file system that maps host side or file system logical block addresses (LBAs) to the physical address of the flash memory (logical-to-physical mapping). The LBAs refer to sector numbers and to a mapping unit of 512 bytes. All LBAs that represent the logical size visible to and managed by the file system are mapped to a physical ___location (block ID, page ID and sector ID) of the Flash. As part of the [[wear leveling]] and other flash management algorithms (bad block management, read disturb management, safe flash handling etc.), the physical ___location of an LBA might dynamically change frequently. The mapping units of an FTL can differ so that LBAs are mapped block-, page- or even sub-page-based. Depending on the usage pattern, a finer mapping granularity can significantly reduce the flash wear out and maximize the endurance of a flash based storage media.<ref>{{cite web|url=http://drona.csa.iisc.ernet.in/~gopi/west10/goodson.pdf|title=Design Tradeoffs in a Flash Translation Layer|first1=Garth|last1=Goodson|first2=Rahul|last2=Iyer|archive-url=https://web.archive.org/web/20150623162937/http://drona.csa.iisc.ernet.in/~gopi/west10/goodson.pdf|archive-date=June 23, 2015}}</ref><ref>{{cite web|url=http://flashdba.com/2014/09/17/understanding-flash-the-flash-translation-layer/|title=Understanding Flash: The Flash Translation Layer|date=September 17, 2014}}</ref><ref>{{cite web|url=http://files.iccmedia.com/magazines/basfeb15/basfeb15-p25.pdf|title=New flash management architecture enables MLC for industrial storage|first=Susan|last=Heidrich|date=February 2015}}</ref>