Power Processing Element: Difference between revisions

Revision as of 17:14, 2 April 2020

Revision as of 02:05, 11 May 2020

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* 64-bit, dual-threaded core

* Typical 3.2 GHz typical clockrate

* 32 KB [[CPU cache|L1 Instructioninstruction cache]]

* 32 KB [[CPU cache|L1 Datadata cache]]

* 512 KB Unifiedunified L2 cache, [[Set-associative#Associativity|8-way set associative]] in the PPE variant.

* Compatible with 64-bit PowerPC ISA v.2.02 ([[POWER4]] and [[PowerPC 970]])<ref>{{cite book |last1=Koranne |first1=Sandeep |title=Practical Programming on the Cell Broadband Engine |date=2009 |publisher=Springer Science & Business Media |isbn=9781441903082 |page=17}}</ref>

* [[AltiVec]] [[SIMD]] functionality