Power Processing Element: Difference between revisions

Revision as of 02:07, 11 May 2020

Revision as of 02:08, 11 May 2020

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The PPU runs two [[Thread_(computing)|hardware threads]] simultaneously. The [[Processor register|main registers]] for code execution are duplicated, as are the exception and interrupt-handling registers, and several essential arrays and queues. They can generate exceptions simultaneously, and perform branch prediction on their individual branch histories. The execution engine and caches are not duplicated though - so it is still just a single-core design.<ref>[https://www.springer.com/cda/content/document/cda_downloaddocument/9781441903075-c1.pdf Chapter 2 - The Power Processing Element (PPE)]</ref>

== Floating Pointpoint Capacitycapacity ==

Its [[64-bit]] [[Doubledouble-precision floating-point format|double precision]] floating-point unit, and [[128-bit]] VMX unit (using the [[AltiVec]] instruction set), can perform a theoretical 12 floating-point operations per cycle, as its floating-point unit can do floating-point multiply-adds, and come no smaller than 64-bits. That gives 3.2 billion clock cycles *× 12 = 38.4 billion floating-point operations/second.

The PPU is enhanced in the [[Cell processor#PowerXCell 8i|PowerXCell 8i]] processor to be able to make single cycle [[Double-precision floating-point format|double precision floating point]] operations, tailored for high performance computing in supercomputers.

The VMX unit in the [[Xenon (processor)|XCPU]] in the Xbox 360 is enhanced with 128 [[Processor register|registers]] and is not entirely compatible with regular AltiVec.