Revision as of 02:24, 11 May 2020 edit 89.107.6.24 (talk) No edit summary ← Previous edit		Revision as of 02:31, 11 May 2020 edit undo 89.107.6.24 (talk) →SPE floorplan Next edit →
Line 81: \| channel \|\| 6.75 \|\| channel interface (three discrete blocks) \|\| odd \|- \| ~~LS0-LS3~~LS0–LS3 \|\| 30.0 \|\| four 64 KiB blocks of local store \|\| odd \|- \| MMU \|\| 4.75 \|\| memory management unit

Cell microprocessor implementations: Difference between revisions