XCore Architecture: Difference between revisions

Revision as of 05:37, 16 March 2020

Revision as of 01:23, 14 June 2020

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| bits = 32-bit

| introduced = 2007

| version = XS1, XS2, XS3

| design = [[RISC]]

| type = [[Load-store architecture|Load-store]]

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| endianness = Little

| gpr = 12

| fpr = 012 (shared, XS3)

| vpr = 3 (256-bit, XS3)

}}

The '''XCore Architecture''' is a 32-bit RISC microprocessor architecture designed by [[XMOS]]. The architecture is designed to be used in [[multi-core processor]]s for [[embedded system]]s. Each XCore executes up to eight concurrent threads, each thread having its own register set, and the architecture directly supports inter-thread and inter-core communication and various forms of thread scheduling.

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==Versions and Devices==

There are twothre versions of the xCORE architecture: XS1, XS2, and XS2XS3; XS2 extendingextends the XS1 architecture, and XS3 extends the XS2 architecture.

===XS1===

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A few instructions have been added to aid in high bandwidth processing, such as dual-word load/store, dual-word zip and unzip (bit and byte strings), dual word arithmetic saturation and shift.

===XS3===

The XS3 architecture was introduced in 2020. It is implemented by a new series of [[xcore.ai]] processors aimed at embedded and IoT devices utilizing [[Artificial_intelligence|AI]] acceleration in [[System_on_a_chip|SoC]]-like designs.

XS3 extends the XS2 architecture with additional [[Digital_signal_processing|DSP]] performance, new 32-bit [[Floating-point_arithmetic|floating-point]] capability, and 256-bit-wide [[Vector_processor|vector]] instructions. Processors based on this architecture also support a two-lane [[MIPI_Alliance|MIPI]] interface for cameras or other sensor input, as well as a 16-bit-wide [[LPDDR]] interface for external [[Dynamic_random-access_memory|DRAM]]. Core clock speed has been increased to 800 MHz, and up to four xCONNECT links are available, providing scalability through the connection of additional xCORE processors.<ref>{{cite web

|title=XMOS announces world’s lowest cost, most flexible AI processor

|url=https://www.xmos.com/xmos-announces-worlds-lowest-cost-most-flexible-ai-processor

|publisher=[[XMOS]]}}</ref>

Of particular note, the new vector capability provides up to 51 GOPS (billion operations per second, e.g. [[Multiply–accumulate_operation|multiply-accumulate]]) of AI performance using 8-bit data, and up to 408 GOPS on binarized (1-bit) neural networks.<ref>{{cite web

|title=XMOS adapts Xcore into AIoT ‘crossover processor’

|url=https://www.eetimes.com/xmos-adapts-xcore-into-aiot-crossover-processor

|publisher=[[XMOS]]}}</ref><ref>{{cite web

|title=Insightful analysis of xcore.ai from The Linley Group

|url=https://www.xmos.com/insightful-analysis-of-xcore-ai |url-access=registration

|publisher=[[The Linley Group]]}}</ref>

==Architecture==