XCore Architecture: Difference between revisions

Revision as of 15:28, 14 June 2020

Revision as of 15:46, 14 June 2020

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===I/O and timing instructions===

The XS1 architecture is event-driven. It has an instruction that can dispatch anon external [[Event (computing)|events]] in addition to traditional [[interrupts]]. If the program chooses to use events, then the underlying processor has to expect an event and wait in a specific place so that it can be handled synchronously. If desired, I/O can be handled asynchronously using interrupts. Events and interrupts can be used on any resource that the implementation supports.

Common resources that are supported are ports (for external input and output), timers (that allow timing to a reference clock), channels (that allow communication and synchronization between threads within a core, and threads on different cores), locks (which allow controlled access to shared memory), and synchronizers (which implement barrier synchronizations between threads).