Soft microprocessor: Difference between revisions

Revision as of 15:05, 19 July 2020

Revision as of 18:12, 20 July 2020

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| 32-bit, RISC-V / MIPS ISA subsets (retargetable), GCC toolchain

| [https://github.com/f32c/f32c f32c]

| VHDL

|-

| [https://github.com/stnolting/neorv32 NEORV32]

| Stephan Nolting

| {{yes|BSD}}

| Wishbone b4

| rv32[i/e][m][c] + privileged ISA RISC-V-compliant CPU, customizable peripherals/SoC, GCC toolchain

| [https://github.com/stnolting/neorv32 GitHub] [https://opencores.org/projects/neorv32 OpenCores]

| VHDL

|-