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* [[Static timing analysis]] (STA) – Slowly being superseded by [[statistical static timing analysis]] (SSTA), STA is used to verify if all the logic data paths in the design can work at the intended [[clock frequency]], especially under the effects of [[Process corners|on-chip variation]]. STA is run as a replacement for [[SPICE]], because SPICE simulation's runtime makes it infeasible for full-chip analysis modern designs.
* [[Electromigration]] lifetime checks – To ensure a minimum lifetime of operation at the intended clock frequency without the circuit succumbing to electromigration.
*[[Functional verification|Functional]] Static Sign-off checks – which use search and analysis techniques to check for design failures under all possible test cases; functional static sign-off domains include [[clock ___domain crossing]], reset ___domain crossing and X-propagation.
== Tools ==
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