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m →Exceptions: Add link to the translation lookaside buffer article section about TLB misses |
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Suppose the CPU is executing the following piece of code:
<syntaxhighlight lang="nasm">
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The instruction fetch and decode stages send the second instruction one cycle after the first. They flow down the pipeline as shown in this diagram:
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However, consider the following instructions:
<syntaxhighlight lang="nasm">
AND r10,r3 -> r11
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The data read from the address <code>adr</code> is not present in the data cache until after the Memory Access stage of the <code>LD</code> instruction. By this time, the <code>AND</code> instruction is already through the ALU. To resolve this would require the data from memory to be passed backwards in time to the input to the ALU. This is not possible. The solution is to delay the <code>AND</code> instruction by one cycle. The data hazard is detected in the decode stage, and the fetch and decode stages are '''stalled''' - they are prevented from flopping their inputs and so stay in the same state for a cycle. The execute, access, and write-back stages downstream see an extra no-operation instruction (NOP) inserted between the <code>LD</code> and <code>AND</code> instructions.
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