Classic RISC pipeline: Difference between revisions

Revision as of 16:56, 11 September 2020

Revision as of 08:33, 14 September 2020

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The instructions reside in memory that takes one cycle to read. This memory can be dedicated SRAM, or an Instruction [[Cache (computing)|Cache]]. The term "latency" is used in computer science often, and means the time from when an operation starts until it completes. Thus, instruction fetch has a latency of one [[clock cycle]] (if using single cycle SRAM or if the instruction was in the cache). Thus, during the [[Instruction fetch|Instruction Fetch]] stage, a 32-bit instruction is fetched from the instruction memory.

The [[Program Counter]], or PC, is a register that holds the address that is presented to the instruction memory. At the start of a cycle, the address is presented to instruction memory. Then during the cycle, the instruction is being read out of instruction memory, and at the same time a calculation is done to determine the next PC. The calculation of the next PC is done by incrementing the PC by 4, and by choosing whether to take that as the next PC or alternatively to take the result of a branch / jump calculation as the next PC. Note that in classic RISC, all instructions have the same length. (This is one thing that separates RISC from CISC <ref>{{cite paperdocument |first=David |last=Patterson| title=RISC I: A Reduced Instruction Set VLSI Computer |url=https://dl.acm.org/doi/10.5555/800052.801895}}</ref>). In the original RISC designs, the size of an instruction is 4 bytes, so always add 4 to the instruction address, but don't use PC + 4 for the case of a taken branch, jump, or exception (see '''delayed branches''', below). (Note that some modern machines use more complicated algorithms ([[branch prediction]] and [[branch target predictor|branch target prediction]]) to guess the next instruction address.)

===Instruction decode===

Another thing that separates the first RISC machines from earlier CISC machines, is that RISC has no [[microcode]] <ref>{{cite paperdocument |first=David |last=Patterson| title=RISC I: A Reduced Instruction Set VLSI Computer |url=https://dl.acm.org/doi/10.5555/800052.801895}}</ref>. In the case of CISC micro-coded instructions, once fetched from the instruction cache, the instruction bits are shifted down the pipeline, where simple combinational logic in each pipeline stage produces control signals for the datapath directly from the instruction bits. In those CISC designs, very little decoding is done in the stage traditionally called the decode stage. A consequence of this lack of decoding is that more instruction bits have to be used to specifying what the instruction does. That leaves fewer bits for things like register indices.

All MIPS, SPARC, and DLX instructions have at most two register inputs. During the decode stage, the indexes of these two registers are identified within the instruction, and the indexes are presented to the register memory, as the address. Thus the two registers named are read from the [[register file]]. In the MIPS design, the register file had 32 entries.

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== References ==

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* {{cite book |firstfirst1=John L. |lastlast1=Hennessy |first2=David A. |last2=Patterson |title=Computer Architecture, A Quantitative Approach |publisher=Morgan Kaufmann |edition=5th |year=2011 |isbn=978-0123838728 |pages= |url=https://books.google.com/books?id=v3-1hVwHnHwC&printsec=frontcover}}

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