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Line 5: [[picoJava]] was the first attempt by [[Sun Microsystems]] to build a Java processor ~~[http://www.imsystech.com/~~ Cjip] from Imsys Technologies. Available on boards and with wireless radios from ~~[http://www.avidwireless.com/AVIDdirector.html~~ AVIDwireless]<ref>"Imsys hedges bets on Java: [[microcode#Writable_control_stores \| rewritable-microcode]] chip has instruction sets for Java, Forth, C/C++"]▼ [https://web.archive.org/web/20101212022901/http://www.ajile.com/index.php?option=com_content&view=article&id=2&Itemid=6 aJ102] and [https://web.archive.org/web/20101212022737/http://ajile.com/index.php?option=com_content&view=article&id=3&Itemid=7 aJ200] from aJile Systems, Inc. Available on boards from [https://web.archive.org/web/20060221235030/http://jstamp.systronix.com/ Systronix] ▲[http://www.imsystech.com/ Cjip] from Imsys Technologies. Available on boards and with wireless radios from [http://www.avidwireless.com/AVIDdirector.html AVIDwireless]<ref>"Imsys hedges bets on Java: [[microcode#Writable_control_stores \| rewritable-microcode]] chip has instruction sets for Java, Forth, C/C++"] by Tom R. Halfhill [http://www.imsystech.com/press_room/press_archive/press_micro_p_report.pdf] {{Webarchive\|url=https://web.archive.org/web/20081119232421/http://www.imsystech.com/press_room/press_archive/press_micro_p_report.pdf \|date=2008-11-19 }}</ref> [https://web.archive.org/web/20060813133121/http://ipr.ira.uka.de/komodo/komodoEng.html Komodo] is a multithreaded Java microcontroller for research on real-time scheduling [http://www.inf.ufrgs.br/en/ FemtoJava] is a research project to build an application specific Java processor [[ARM9E\|ARM926EJ-S]] is an ARM processor able to run Java bytecode, this technology being named ''[[Jazelle]]'' [[Java Optimized Processor]]<ref>{{Cite journal\| first1 = M.\| title = A Java processor architecture for embedded real-time systems\| last1 = Schoeberl\| journal = Journal of Systems Architecture\| volume = 54\| issue = 1–2\| pages = 265–286\| year = 2008 \| doi = 10.1016/j.sysarc.2007.06.001\| citeseerx = 10.1.1.68.8757}}</ref> for [[FPGA]]s. A PhD thesis is [https://web.archive.org/web/20120204093123/http://www.jopdesign.com/thesis/index.jsp available] jHISC<ref>{{Cite journal\| doi = 10.1016/j.micpro.2005.12.007\| title = A Java processor with hardware-support object-oriented instructions\| year = 2006\| last1 = Yiyu \| first1 = T.\| last2 = Wanyiu \| first2 = L.\| last3 = Chihang \| first3 = Y.\| last4 = Li \| first4 = R.\| last5 = Fong \| first5 = A.\| journal = Microprocessors and Microsystems\| volume = 30\| issue = 8\| pages = 469 }}</ref> provides hardware support for object-oriented functions▼ [https://web.archive.org/web/20120210170652/http://shap.inf.tu-dresden.de/ SHAP] bytecode processor from the TU Dresden ▲<ref>{{Cite journal\| doi = 10.1016/j.micpro.2005.12.007\| title = A Java processor with hardware-support object-oriented instructions\| year = 2006\| last1 = Yiyu \| first1 = T.\| last2 = Wanyiu \| first2 = L.\| last3 = Chihang \| first3 = Y.\| last4 = Li \| first4 = R.\| last5 = Fong \| first5 = A.\| journal = Microprocessors and Microsystems\| volume = 30\| issue = 8\| pages = 469 }}</ref> provides hardware support for object-oriented functions ObjectCore is a multicore Java processor designed by Vivaja Technologies. *Java Offload Engine (JOE) is a high performance Java co-processor from Temple Computing Labs LLP. ==References==

Java processor: Difference between revisions