512-bit computing: Difference between revisions

Revision as of 10:21, 23 September 2020

Revision as of 10:21, 23 September 2020

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==Uses==

[[File:Sapphire Radeon R9 290X-front oblique PNr°0437.jpg|thumb|The AMD [[Radeon R9]] 290X (Sapphire OEM version pictured here) uses a 512 bit memory bus]]

* Some GPUs such as the [[AMD]] [[Radeon_HD_2000_series#Radeon_HD_2900|Radeon HD 2900XT]], the [[Nvidia]] GTX 280,<ref>{{cite web|url=http://www.geforce.com/hardware/desktop-gpus/geforce-gtx-280/specifications |title=GTX 280 &#124; Specifications |publisher=GeForce |date= |accessdate=2013-08-13}}</ref> GTX 285,<ref>{{cite web|url=http://www.geforce.com/hardware/desktop-gpus/geforce-gtx-285/specifications |title=GTX 285 &#124; Specifications |publisher=GeForce |date= |accessdate=2013-08-13}}</ref> Quadro FX 5800<ref>{{cite web|url=http://www.nvidia.com/ofreeobject/product_quadro_fx_5800_us.html joseph|title=NVIDIA® Quadro® FX 5800 provides professionals with visual supercomputing from their desktops delivering results that push visualization beyond traditional 3D |publisher=Nvidia.com |date= |accessdate=2013-08-13}}</ref> and several [[Nvidia Tesla]] products move data across a 512-bit memory bus. Then [[AMD Radeon Rx 200 Series#Radeon R9 290|AMD Radeon R9 290, R9 290X and 295X2]] followed.

* Many [[hash functions]], such as [[SHA-512]] and [[SHA3-512]], have a 512-bit output.

* [[AVX-512]] are 512-bit extensions to the 256-bit [[Advanced Vector Extensions]] SIMD instructions for x86 [[instruction set architecture]] proposed by Intel in July 2013, and released on 2016 with [[Xeon Phi#Knights Landing|Knights Landing]], and in 2018 on the HEDT and consumer server platform, with Skylake-X and [[Skylake (microarchitecture)#"Skylake-SP" (14 nm) Scalable Performance|Skylake-SP]] respectively.

==References==

{{reflist}}