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# H [[Half-carry flag]]. This is an internal carry from additions and is used to support [[Binary-coded decimal|BCD]] arithmetic.
# T Bit copy. Special bit load and bit store instructions use this bit.
# I [[Interrupt flag]]. Set when interrupts are enabled
== Addressing ==
The following address spaces are available:
* The general purpose registers are addressed by their numbers (0–31), although the full 5-bit number is not stored in instructions that can only operate on a subset of those registers.
* I/O registers have a dedicated 6-bit address space, the lower half of which is bit-addressable; some parts have I/O registers outside this address space, which are called "extended I/O" and are only accessible as [[memory-mapped I/O]] in the data address space.
* The data address space maps the 32 general-purpose registers, all the I/O registers (including those also accessible through the I/O address space), and the RAM; it can be addressed either directly or indirectly through the X, Y and Z pointer registers, prepended if necessary by RAMPX, RAMPY and RAMPZ respectively.
* Program memory ([[Flash memory|flash]]) has a separate address space, addressed as 16-bit words for the purpose of fetching instructions
* For the purpose of fetching constant data, program memory is addressed bytewise through the Z pointer register, prepended if necessary by RAMPZ.
* The [[EEPROM]] is memory-mapped in some devices; in others, it is not directly addressable and is instead accessed through address, data and control I/O registers.
* The general purpose registers, the status register and some I/O registers are bit-addressable, with bit 0 being the least significant and bit 7 the most significant.
The first 64 I/O registers are accessible through both the I/O and the data address space. They have therefore two different addresses. These are usually written as "0x00 (0x20)" through "0x3F (0x5F)", where the first item is the I/O address and the second, in parentheses, the data address.
The special-purpose CPU registers, with the exception of PC, can be accessed as I/O registers. Some registers (RAMPX, RAMPY) may not be present on machines with less than 64 [[KiB]] of addressable memory.
{| class="wikitable"
! Register !! I/O address !! Data address
|-
| SREG || 0x3F || 0x5F
|-
| SP || 0x3E:0x3D || 0x5E:0x5D
|-
| EIND || 0x3C || 0x5C
|-
| RAMPZ || 0x3B || 0x5B
|-
| RAMPY || 0x3A || 0x5A
|-
| RAMPX || 0x39 || 0x59
|-
| RAMPD || 0x38 || 0x58
|}
A typical ATmega memory map may look like:
{| class="wikitable"
! Data address !! I/O address !! Contents
|-
| 0x0000 – 0x001F || || Registers R0 – R31
|-
| 0x0020 – 0x003F || 0x00 – 0x1F || I/O registers (bit-addressable)
|-
| 0x0040 – 0x005F || 0x20 – 0x3F || I/O registers (not bit-addressable)
|-
| 0x0060 – 0x00FF || || Extended I/O registers (memory-mapped I/O only)
|-
| 0x0100 – RAMEND || || Internal SRAM
|}
where RAMEND is the last RAM address. In parts lacking extended I/O the RAM would start at 0x0060.
== Instruction timing ==
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