Revision as of 06:05, 23 April 2020 edit SUM1 (talk \| contribs) Autopatrolled, Extended confirmed users, Template editors 37,430 edits m Grammar Tag: Visual edit ← Previous edit		Revision as of 08:30, 23 October 2020 edit undo 79.16.14.91 (talk) →AMD Zen 2 microarchitecture (2019): Zen 2 CCXs have 4 cores, not 8 (like Zen 3). Tags: Mobile edit Mobile web edit Next edit →
Line 107: * L1 cache – 32 kB data & 32 kB instruction per core, 8-way * L2 cache – 512 kB per core, 8-way inclusive * L3 cache – 16 MB local per 84-core CCX, 2 CCXs per chiplet, 16-way non-inclusive. Up to 64 MB on desktop CPUs and 256 MB on server CPUs === IBM Power 7 ===

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