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The '''floating body effect''' is the effect of dependence of the body potential of a [[transistor]] realized by the [[silicon on insulator]] (SOI) technology on the history of its biasing and the [[carrier recombination]] processes. The transistor's body forms a capacitor against the insulated substrate. The charge accumulates on this capacitor and may cause adverse effects, for example, opening of parasitic transistors in the structure and causing off-state leakages, resulting in higher current consumption and in case of [[dynamic random access memory|DRAM]] in loss of information from the memory cells. It also causes the '''history effect''', the dependence of the [[threshold voltage]] of the transistor on its previous states. In analog devices, the floating body effect is known as the '''kink effect'''.
One countermeasure to floating body effect involves use of fully depleted (FD) devices. The insulator layer in FD devices is significantly thinner than the channel depletion width. The charge and thus also the body potential of the transistors is therefore fixed.<ref>{{cite journal | last=Shahidi | first=G. G. | title=SOI technology for the GHz era | journal=IBM Journal of Research and Development | publisher=IBM | volume=46 | issue=2.3 | year=2002 | issn=0018-8646 | doi=10.1147/rd.462.0121 | pages=121–131}}</ref> However, the short-channel effect is worsened in the FD devices, the body may still charge up if both source and drain are high, and the architecture is unsuitable for some analog devices that require contact with the body.<ref>{{cite web|url=https://www.eetimes.com/document.asp?doc_id=1144089|title=Intel Does About-Face on SOI, Backs High-k Dielectric|website=[[EE Times]]|___location=Stanford, California|first=Anthony|last=Cataldo|date=2001-11-26|accessdate=2019-03-30}}</ref> Hybrid trench isolation is another approach.<ref>{{cite web|url=https://www.eetimes.com/document.asp?doc_id=1204577|title=Mitsubishi SOI Process Uses Hybrid Trench Isolation|website=EE Times|___location=Makuhari, Japan|first=Paul|last=Kallender|date=2001-12-17|accessdate=2019-03-30}}</ref>
While floating body effect presents a problem in SOI DRAM chips, it is exploited as the underlying principle for [[Z-RAM]] and [[T-RAM]] technologies. For this reason, the effect is sometimes called the '''Cinderella effect''' in the context of these technologies, because it transforms a disadvantage into an advantage.<ref>[http://www.onversity.net/load/zram.pdf Z-RAM Shrinks Embedded Memory], [[Microprocessor Report]]</ref> [[AMD]] and [[Hynix]] licensed Z-RAM, but as of 2008 had not put it into production.<ref name="Intel explores" /> Another similar technology (and Z-RAM competitor) developed at Toshiba<ref>{{cite web|url=https://spectrum.ieee.org/semiconductors/memory/winner-masters-of-memory|title=Winner: Masters of Memory Swiss firm crams 5 megabytes of RAM into the space of one|date=1 Jan 2007|accessdate=23 Mar 2019|author=Samuel K. Moore|website=IEEE Spectrum}}</ref><ref>{{cite web|url=http://www.eetimes.com/document.asp?doc_id=1144452|title=Toshiba cuts capacitor from DRAM cell design|author=Yoshiko Hara|date=7 Feb 2002|website=[[EE Times]]|accessdate=23 Mar 2019}}</ref> and refined at Intel is [[Floating Body Cell]] (FBC).<Ref>{{cite web|url=http://www.theinquirer.net/inquirer/news/1006279/intel-talks-up-floating-body-cells|title=Intel talks up Floating Body Cells|author=Nick Farrell|date=11 Dec 2006|accessdate=23 Mar 2019|website=The Inquirer}}</ref><ref name="Intel explores">{{cite web|url=http://www.eetimes.com/document.asp?doc_id=1168759|title=Intel explores floating-body cells on SOI|author=Mark LaPedus|date=17 Jun 2008|accessdate=23 May 2019|website=[[EE Times]]}}</ref>
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