Cache hierarchy: Difference between revisions

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AMD Zen 2 microarchitecture (2019): Zen 2 CCXs have 4 cores, not 8 (like Zen 3).
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*L1 cache, AAT = 1 ns + (0.1 × 50 ns) = 6 ns
*L1–2 caches, AAT = 1 ns + (0.1 × [5 ns + (0.01 × 50 ns)]) = 1.55 ns
*L1–3 caches, AAT = 1 ns + (0.1 × [5 ns + (0.01 × [10 ns + (0.002 × 50 ns)])]) = 1.50015101 ns
 
=== Disadvantages ===