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== Single-level cell ==
[[Flash memory]] stores data in individual memory cells, which are made of [[floating-gate MOSFET]] transistors. Traditionally, each cell had two possible states (each with one voltage level), with each state representing either a one or a zero so one [[bit]] of data was stored in each cell in so-called ''single-level cells'', or SLC flash memory. SLC memory has the advantage of higher write speeds, lower power consumption and higher cell endurance. However, because SLC memory stores less data per cell than MLC memory, it costs more per megabyte of storage to manufacture. Due to higher transfer speeds and expected longer life, SLC flash technology is used in high-performance [[memory card]]s.
In February 2016, a study was published that showed little difference in practice between the reliability of SLC and MLC.<ref>{{Cite journal |title= Flash Reliability in Production: The Expected and the Unexpected |author= Bianca Schroeder and Arif Merchant |publisher= Usenix |journal= Conference on File and Storage Technologies |date= February 22, 2016 |url= https://www.usenix.org/conference/fast16/technical-sessions/presentation/schroeder |accessdate= November 3, 2016 }}</ref>
A single-level cell (SLC) Flash memory may have a lifetime of about 50,000 to 100,000 program/erase cycles.<ref>https://www.hyperstone.com/en/NAND-Flash-is-displacing-hard-disk-drives-1249,12728.html, NAND Flash is displacing Hard Disk Drives, Retrieved 29. May 2018</ref>
A single level cell represents a 1 when almost empty and a 0 when almost full. There is a region of uncertainty between the two possible states at which the data stored in the cell cannot be precisely read.<ref name="anandtech"/>
== Multi-level cell ==
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The [[Intel 8087]] used two-bits-per-cell technology, and in 1980 was one of the first devices on the market to use multi-level ROM cells.<ref>"Four-state cell called density key" article by J. Robert Lineback. "Electronics" magazine. 1982 June 30.</ref><ref>P. Glenn Gulak. [https://pdfs.semanticscholar.org/a3c1/cbc425c7987fe2307b48e0ff96f2c2c1b038.pdf "A Review of Multiple-Valued Memory Technology"]</ref> [[Intel]] later demonstrated 2-bit multi-level cell (MLC) [[NOR flash]] in 1997.<ref name="Smithsonian">{{cite web |title=The Flash Memory Market |url=http://smithsonianchips.si.edu/ice/cd/MEMORY97/SEC05.PDF |website=Integrated Circuit Engineering Corporation |publisher=[[Smithsonian Institution]] |year=1997 |accessdate=16 October 2019}}</ref> [[NEC]] demonstrated quad-level cells in 1996, with a 64{{nbsp}}[[Mebibit|Mb]] [[flash memory]] chip storing 2-bit per cell. In 1997, NEC demonstrated a [[dynamic random-access memory]] (DRAM) chip with quad-level cells, holding a capacity of 4{{nbsp}}Gb. [[STMicroelectronics]] also demonstrated quad-level cells in 2000, with a 64{{nbsp}}Mb [[NOR flash]] memory chip.<ref name="stol">{{cite web |title=Memory |url=http://maltiel-consulting.com/Semiconductor_technology_memory.html |website=STOL (Semiconductor Technology Online) |accessdate=25 June 2019}}</ref>
MLC is used to refer to cells that store two bits per cell, using four charge values or levels. A 2-bit MLC has a single charge level assigned to every possible combination of ones and zeros, as follows: When close to 25% full, the cell represents a binary value of 11, when close to 50% the cell represents a 01, when close to 75% the cell represents a 00, and when close to 100% the cell represents a 10. Once again, there is a region of uncertainty between values, at which the data stored in the cell cannot be precisely read.<ref>https://www.enterprisestorageforum.com/storage-hardware/slc-vs-mlc-vs-tlc-nand-flash.html</ref><ref name="anandtech">https://www.anandtech.com/show/4902/intel-ssd-710-200gb-review/2</ref>
{{As of|2013|post=,}} some [[solid-state drives]] use part of an MLC NAND die as if it were single-bit SLC NAND, giving higher write speeds.<ref>Geoff Gasior. [http://techreport.com/review/25122/samsung-840-evo-solid-state-drive-reviewed "Samsung's 840 EVO solid-state drive reviewed: TLC NAND with a shot of SLC cache"]. 2013.</ref><ref>Allyn Malventano. [http://www.pcper.com/news/Storage/New-Samsung-840-EVO-employs-TLC-and-pseudo-SLC-TurboWrite-cache "New Samsung 840 EVO employs TLC and pseudo-SLC TurboWrite cache"]. 2013.</ref><ref>Samsung. [http://www.samsung.com/global/business/semiconductor/samsungssd/downloads/Samsung_SSD_TurboWrite_Whitepaper.pdf "Samsung Solid State Drive: TurboWrite Technology White Paper"]. 2013.</ref>
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