Routing (electronic design automation): Difference between revisions

Revision as of 00:39, 10 August 2020

Revision as of 00:05, 12 December 2020

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<ref name="Hadlock_1977">{{cite journal |author-first=Frank O. |author-last=Hadlock |title=A shortest path algorithm for grid graphs |journal=Networks |date=1977-12-01 |volume=7 |number=4 |pages=323–334 |doi=10.1002/net.3230070404 |url=https://www.researchgate.net/publication/227815552}}</ref>

<ref name="SimplifyPCB">{{Cite web | url=http://www.simplifyda.com |title = Simplify Design Automation – the next generation in design methodology}}</ref>

<ref name="Pfeil_2017_Bloodhound">{{cite journal |title=A lifetime designing PCBs: From design to software |author-first=Charles |author-last=Pfeil |date=2017-11-02 |journal=[[EDN Network]] |url=https://www.edn.com/electronics-blogs/all-aboard-/4459033/A-lifetime-designing-PCBs--From-design-to-software |access-date=2018-10-20 |url-status=live |archive-url=https://web.archive.org/web/20181021225546/https://www.edn.com/electronics-blogs/all-aboard-/4459033/A-lifetime-designing-PCBs--From-design-to-software |archive-date=2018-10-21<!-- -->}}</ref>

<ref name="CW_1992_Bloodhound">{{cite journal |title=Computer-Partner Kiel GmbH: "Bloodhound" entflechtet Leiterplatten auf 16 Lagen |language=Germande |journal=[[Computerwoche]] |date=1992-03-13 |url=https://www.computerwoche.de/a/bloodhound-entflechtet-leiterplatten-auf-16-lagen,1133225 |access-date=2018-10-20 |url-status=live |archive-url=https://archive.today/20181021231138/https://www.computerwoche.de/a/bloodhound-entflechtet-leiterplatten-auf-16-lagen,1133225 |archive-date=2018-10-21}}</ref>

<ref name="Redlich_2018_Routers">{{cite book |title=Schaltungsdesign |author-first=Detlef |author-last=Redlich |chapter=1.6. Rechnergestützter Leiterplattenentwurf - Entflechtung |language=Germande |publisher=[[Ernst-Abbe-Hochschule Jena]] (EAH) |chapter-url=http://web.eah-jena.de/fhj/etit/fb/homepage/home-redlich/lehre/design/Documents/Rechnergest_LP_Entwurf_Einf%C3%BChrung.pdf |access-date=2018-10-20 |url-status= |archive-url=https://archive.today/20181021231530/http://web.eah-jena.de/fhj/etit/fb/homepage/home-redlich/lehre/design/Documents/Rechnergest_LP_Entwurf_Einf%C3%BChrung.pdf |archive-date=2018-10-21}}</ref>

<ref name="Webb_2012">{{cite web |title=A Tribute to Alan Finch, the Father of Gridless Autorouting |author-first=Darrell |author-last=Webb |date=2012-12-20 |url=https://blog.zuken.com/a-tribute-to-alan-finch-the-father-of-gridless-autorouting/ |access-date=2018-10-22 |url-status=live |archive-url=https://archive.today/20181022034218/https://blog.zuken.com/a-tribute-to-alan-finch-the-father-of-gridless-autorouting/ |archive-date=2018-10-22}}</ref>

<ref name="Finch_1985">{{cite conference |author-first1=Alan C. |author-last1=Finch |author-first2=Ken J. |author-last2=Mackenzie |author-first3=G. J. |author-last3=Balsdon |author-first4=G. |author-last4=Symonds |title=A Method for Gridless Routing of Printed Circuit Boards |journal=Design Automation Conference, 2009. Dac '09. 46Th Acm/IEEE |conference=22nd ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA |date=1985-06-23<!-- /26 --> |publisher=[[Racal-Redac Ltd.]] |___location=Newtown, Tewkesbury, Gloucestershire, UK |issn=0738-100X |isbn=0-8186-0635-5 |pages=509–515 |doi=10.1109/DAC.1985.1585990 |url=https://www.cs.york.ac.uk/rts/docs/DAC-1964-2006/PAPERS/1985/DAC85_509.PDF |access-date=2018-10-22 |url-status=live |archive-url=https://web.archive.org/web/20181022030533/https://www.cs.york.ac.uk/rts/docs/DAC-1964-2006/PAPERS/1985/DAC85_509.PDF |archive-date=2018-10-22}}</ref>