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===Balance FPGA Resources While Creating Design Partitions===
When creating circuit partitions, engineers should first observe the available resources the FPGA offers, since the design will be placed onto the FPGA fabric.<ref name="Aldec" /> The architecture of each FPGA is dependent on the manufacturer, but the main goal in design partitioning is to have an even balance of FPGA resource utilization. Various FPGA resources include [[Lookup table|lookup tables]] (LUTs), [[D flip-flops]], block [[Random-access memory|RAMs]], [[Digital signal processor|digital signal processors]] (DSPs), clock buffers, etc. Prior to balancing the design partitions, it is also valuable to the user to perform global [[logic optimization]] to remove any redundant or unused logic. A typical problem that arises with creating balanced partitions is that it may lead to timing or resource conflict if the cut is on many signal lines. To have a fully optimized partitioning strategy, the engineer must consider issues such as timing/power constraints and placement and routing while still maintaining a balanced partition amongst the FPGAs. Strictly focusing on a single issue during a partition may create several issues in another.
===Placing and Routing Partitions===
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