Cache placement policies: Difference between revisions

Revision as of 17:29, 23 November 2020

Revision as of 01:37, 22 December 2020

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== Direct-mapped cache ==

In a direct-mapped cache structure, the cache is organized into multiple sets<ref name=":0" /> with a single cache line per set. Based on the address of the memory block, it can only occupy a single cache line. The cache can be framed as a (n*1) column matrix.<ref name=":1">{{Cite book|title=Fundamentals of Parallel Multi-core Architecture|last=Solihin|first=Yan|publisher=Taylor & Francis|year=2015|isbn=978-1482211184|___location=|pages=136–141|quote=|via=}}</ref>

=== To place a block in the cache ===

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=== Disadvantage ===

* It has lower cache hit rate, as there is only one cache line available in a set. Every time a new memory is referenced to the same set, the cache line is replaced, which causes conflict miss.<ref>{{Cite web|url=http://meseec.ce.rit.edu/eecc551-winter2001/551-1-30-2002.pdf|title=Cache Miss Types|last=|first=|date=|website=|publisher=|access-date=}}</ref>

=== Example ===

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* The cache line is selected based on the valid bit<ref name=":0" /> associated with it. If the valid bit is 0, the new memory block can be placed in the cache line, else it has to be placed in another cache line with valid bit 0.

* If the cache is completely occupied then a block is evicted and the memory block is placed in that cache line.

* The eviction of memory block from the cache is decided by the replacement policy.<ref>{{Cite web|url=https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Memory/fully.html|title=Fully Associative Cache|last=|first=|date=|website=|publisher=|access-date=}}</ref>

=== To search a word in the cache ===