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Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to an [[Field-programmable gate array]] (FPGA) or during the chip synthesis.
ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014. </ref> or video coding.<ref> Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014 </ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. There are some commercial tools to design ASIPs, for example
==See also==
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==External links==
*[https://www.synopsys.com/dw/ipdir.php?ds=asip-designer ASIP Designer, proprietary tool suite from Synopsys enabling compiler-in-the-loop incremental design of ASIPs]
*[http://tce.cs.tut.fi TTA-Based Codesign Environment (TCE), an open source (MIT licensed) toolset for design of application specific TTA processors.]
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