Content deleted Content added
m →Dynamic logic example: png -> svg |
m Disambiguate Impedance to Electrical impedance using popups; You can help! |
||
Line 15:
The largest difference between static and dynamic logic is that in dynamic logic, a [[clock signal]] is used to evaluate [[combinational logic]]. However, to truly comprehend the importance of this distinction, the reader will need some background on static logic.
In most types of logic design, termed ''static logic'', there is at all times some mechanism to drive the output either high or low. In many of the popular logic styles, such as [[Transistor-transistor logic|TTL]] and traditional [[CMOS]], this principle can be rephrased as a statement that there is always a low-impedance path between the output and either the supply [[voltage]] or the [[ground]]. As a sidenote, there is of course an exception in this definition in the case of high [[Electrical impedance|impedance]] outputs, such as a [[tri-state buffer]]; however, even in these cases, the circuit is intended to be used within a larger system where some mechanism will drive the output, and they do not qualify as distinct from static logic.
In contrast, in ''dynamic logic'', there is not always a mechanism driving the output high or low. In the most common version of this concept, the output is driven high or low during distinct parts of the clock cycle.
| |||