Cellular neural network: Difference between revisions

Revision as of 08:26, 27 December 2020

Revision as of 08:28, 27 December 2020

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Despite their speed and low power consumption, there are some significant drawbacks to analog CNN processors. First, analog CNN processors can potentially create erroneous results due to environment and process variation. In most applications, these errors are not noticeable, but there are situations where minor deviations can result in catastrophic system failures. For example, in chaotic communication, process variation will change the [[trajectory]] of a given system in phase space, resulting in a loss of synchronicity/stability. Due to the severity of the problem, there is considerable research being performed to ameliorate the problem. Some researchers are optimizing templates to accommodate greater variation. Other researchers are improving the semiconductor process to more closely match theoretical CNN performance. Other researchers are investigating different, potentially more robust CNN architectures. Lastly, researchers are developing methods to tune templates to target a specific chip and operating conditions. In other words, the templates are being optimized to match the information processing platform. Not only does process variation limit what can be done with current analog CNN processors, it is also a barrier for creating more complex processing units. Unless this process variation is resolved, ideas such as nested processing units, non-linear inputs, etc. cannot be implemented in a real-time analog CNN processor. Also, the semiconductor "real estate" for processing units limits the size of CNN processors.

Currently the largest AnaVision CNN-based vision processor consists of a 4K detector, which is significantly less than the megapixel detectors found in affordable, consumer cameras. Unfortunately, feature size reductions, as predicted by [[Moore’s Law]], will only result in minor improvements. For this reason, alternate technologies such as Resonant Tunneling Diodes and Neuron-Bipolar Junction Transistors are being explored.<ref>W. AlsoYen and C. Wu, the"The architectureDesign of Neuron-Bipolar Junction Transistor (vBJT) Cellular Neural Network(CNN) processorsStructure with Multi-Neighborhood-Layer Template", Int’l Workshop on Cellular Neural Networks and Their Applications, 2000.</ref> Also, CNN processor architecture is being reevaluatedre-evaluated. For example, Star-CNN processors, where one analog multiplier is time-shared between multiple processor units, have been proposed and are expected to result in processor unit reduction size of eighty80%.<ref>F. Sargeni, V. Bonaiuto and M. Bonifazi, "Multiplexed Star-CNN Architecture", Int’l Workshop on Cellular Neural Networks and Their Applications, percent2006.</ref>

=== Digital CNN processors, FPGA ===

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*A. Paasiot and J. Poilkonent, "Programmable Diital Nested CNN", Int’l Workshop on Cellular Neural Networks and Their Applications, 2006.

*M. Znggi, R. Dogaru, and L. Chua, "Physical Modeling of RTD-Based CNN Cells", Int’l Workshop on Cellular Neural Networks and Their Applications, 2000.

*W. Yen and C. Wu, "The Design of Neuron-Bipolar Junction Transistor (vBJT) Cellular Neural Network(CNN) Structure with Multi-Neighborhood-Layer Template", Int’l Workshop on Cellular Neural Networks and Their Applications, 2000.

*F. Sargeni, V. Bonaiuto and M. Bonifazi, "Multiplexed Star-CNN Architecture", Int’l Workshop on Cellular Neural Networks and Their Applications, 2006.

*Z. Kincsest, Z. Nagyl, and P. Szolgay, "Implementation of Nonlinear Template Runner Emulated Digital CNN-UM on FPGA", Int’l Workshop on Cellular Neural Networks and Their Applications, 2006.

*W. Fangt, C. Wang and L. Spaanenburg, "In Search of a Robust Digital CNN System" Int’l Workshop on Cellular Neural Networks and Their Applications, 2006.