Multi-channel memory architecture: Difference between revisions

Revision as of 11:52, 18 December 2020

Revision as of 12:49, 2 January 2021

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In the fields of [[digital electronics]] and [[computer hardware]], '''multi-channel memory architecture''' is a technology that increases the data transfer rate between the [[DRAM]] memory and the [[memory controller]] by adding more channels of communication between them. Theoretically this multiplies the data rate by exactly the number of channels present. Dual-channel memory employs two channels. The technique goes back as far as the 1960s having been used in [[IBM System/360 Model 91]] and in [[CDC 6600]].<ref name="JacobNg2007">{{cite book| first1=Bruce | last1 = Jacob | first2 = Spencer | last2 = Ng | first3=David | last3 = Wang|title= Memory systems: cache, DRAM, disk|year = 2007 | publisher = Morgan Kaufmann|isbn=978-0-12-379751-3|page= 318}}</ref>

Modern high-end processors like the [[Intel]] [[Core i9]] and [[AMD]] [[Ryzen Threadripper]] series, along with various Intel [[Xeon]]s support quad-channel memory. In March 2010, AMD released [[Socket G34]] and Magny-Cours Opteron 6100 series<ref name = Opteron6100>{{cite web | publisher = AMD | title = Opteron 6000 Series Platform Quick Reference Guide | url = http://sites.amd.com/us/documents/48101a_opteron%20_6000_qrg_rd2.pdf | accessdateaccess-date = 2012-10-15 | archive-url = https://web.archive.org/web/20120512170219/http://sites.amd.com/us/Documents/48101A_Opteron%20_6000_QRG_RD2.pdf | archive-date = 2012-05-12 | url-status = dead }}</ref> processors with support for quad-channel memory. In 2006, Intel released chipsets that support quad-channel memory for its [[LGA771]] platform<ref>{{Citation | url = http://ark.intel.com/products/27746/Intel-5000P-Memory-Controller | publisher = Intel | title = 5000P memory controller}}.</ref> and later in 2011 for its [[LGA2011]] platform.<ref>{{Citation | url = http://www.techpowerup.com/138087/Intel-LGA2011-Socket-X68-Express-Chipset-Pictured.html | title = Intel LGA2011 socket x68 express chipset pictured | publisher = Tech power up}}.</ref> Microcomputer chipsets with even more channels were designed; for example, the chipset in the [[AlphaStation]] 600 (1995) supports eight-channel memory, but the [[backplane]] of the machine limited operation to four channels.<ref>{{Citation | journal = HP | url = http://www.hpl.hp.com/hpjournal/dtj/vol7num1/vol7num1art7.txt | title = The Design and Verification of the AlphaStation 600 5-series Workstation | volume = 7 | number = 1 | author1 = John H. Zurawski | author2 = John E. Murray | author3 = Paul J. Lemmon}}.</ref> <!-- TODO: Cite a machine where they actually used 8 channels. -->

== Dual-channel architecture ==

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=== Operation ===

Dual-channel architecture requires a dual-channel-capable motherboard and two or more [[DDR SDRAM|DDR]], [[DDR2 SDRAM|DDR2]], [[DDR3 SDRAM|DDR3]], [[DDR4 SDRAM|DDR4]], or [[DDR5 SDRAM|DDR5]] memory modules. The memory modules are installed into matching banks, each of which belongs to a different channel. The motherboard's manual will provide an explanation of how to install memory for that particular unit. A matched pair of memory modules may usually be placed in the first bank of each channel, and a different-capacity pair of modules in the second bank.<ref name= "Kingston520DDR">{{cite web | publisher = Infineon Technologies North America and Kingston Technology |date=September 2003 | url = http://www.kingston.com/newtech/MKF_520DDRwhitepaper.pdf | archiveurlarchive-url = https://web.archive.org/web/20110929024052/http://www.kingston.com/newtech/MKF_520DDRwhitepaper.pdf | title = Intel Dual-Channel DDR Memory Architecture White Paper | edition = Rev. 1.0 | format = PDF, 1021&nbsp;[[kilobyte|KB]] | accessdateaccess-date = 2007-09-06 | archivedatearchive-date = 2011-09-29}}</ref> Modules rated at different speeds can be run in dual-channel mode, although the motherboard will then run all memory modules at the speed of the slowest module. Some motherboards, however, have compatibility issues with certain brands or models of memory when attempting to use them in dual-channel mode. For this reason, it is generally advised to use identical pairs of memory modules, which is why most memory manufacturers now sell "kits" of matched-pair DIMMs. Several motherboard manufacturers only support configurations where a "matched pair" of modules are used. A matching pair needs to match in:

* Capacity (e.g. 1024&nbsp;MB). Certain Intel chipsets support different capacity chips in what they call Flex Mode: the capacity that can be matched is run in dual-channel, while the remainder runs in single-channel.

* Speed (e.g. PC5300). If speed is not the same, the lower speed of the two modules will be used. Likewise, the higher latency of the two modules will be used.

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| url = http://www.tweaktown.com/articles/4416/intel_x79_quad_channel_and_z68_dual_channel_memory_performance_analysis/index.html

| title = Intel X79 Quad Channel and Z68 Dual Channel Memory Performance Analysis

| date = 2011-11-16 | accessdateaccess-date = 2013-11-30

| author = Shawn Baker | publisher = [[TweakTown]]

}}</ref>{{rp|p. 5}} Other tests performed by TweakTown on the same subject showed no significant differences in performance, leading to a conclusion that not all benchmark software is up to the task of exploiting increased parallelism offered by the multi-channel memory configurations.<ref name="tweaktown-banchmark" />{{rp|p. 6}}

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| url = http://ixbtlabs.com/articles3/cpu/amd-phenom-x4-9850-ganged-unganged-p1.html

| title = AMD Phenom X4 Memory Controller in the Ganged/ Unganged Mode

| date = 2008-08-16 | accessdateaccess-date = 2014-01-09

| website = ixbtlabs.com

}}</ref> more modern implementations of dual-channel use the "unganged" mode by default, which maintains two 64-bit memory buses but allows independent access to each channel, in support of [[Multithreading (computer architecture)|multithreading]] with [[multi-core processor]]s.<ref name="ilsistemista-phenom">{{Cite web

| url = http://www.ilsistemista.net/index.php/hardware-analysis/3-the-phenom-phenomii-memory-controller-and-the-ganged-vs-unganged-question.html?start=1

| title = The Phenom / PhenomII memory controller: ganged vs unganged mode benchmarked

| date = 2010-06-17 | accessdateaccess-date = 2014-01-09

| author = Gionatan Danti | website = ilsistemista.net

}}</ref><ref name="amd-bkdg-10h">{{Cite web

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| title = BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors

| pages = 107–108

| date = 2013-01-11 | accessdateaccess-date = 2014-01-09

| website = amd.com

| quote = When the DCTs are in ganged mode, as specified by [The DRAM Controller Select Low Register] F2x110 [DctGangEn], then each logical DIMM is two channels wide. Each physical DIMM of a 2-channel logical DIMM is required to be the same size and use the same timing parameters. Both DCTs must be programmed with the same information (see 2.8.1 [DCT Configuration Registers]). When the DCTs are in unganged mode, a logical DIMM is equivalent to a 64-bit physical DIMM and each channel is controlled by a different DCT. Typical systems are recommended to run in unganged mode to benefit from the additional parallelism generated by using the DCTs independently. See 2.12.2 [DRAM Considerations for ECC] for DRAM ECC implications of ganged and unganged mode. Ganged mode is not supported for S1g3, S1g4, ASB2, and G34 processors.}}</ref>

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| title = JBOD (just a bunch of disks or just a bunch of drives)

| url = http://searchstorage.techtarget.com/definition/JBOD

| date = September 2005 | accessdateaccess-date = 2014-01-09

| first = Margaret | last = Rouse

| website = SearchStorage.TechTarget.com

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'''AMD Opteron:'''

* Opteron 6100-series "Magny-Cours" (45&nbsp;nm)<ref name="Opteron6100"/>

* Opteron 6200-series "Interlagos" (32&nbsp;nm)<ref name=Opteron6200>{{cite web | title = AMD Opteron 6200 Series Processor Quick Reference Guide | url = https://www.amd.com/us/Documents/Opteron_6000_QRG.pdf | accessdateaccess-date = 2012-10-15 }}</ref>

* Opteron 6300-series "Abu Dhabi" (32&nbsp;nm)<ref name=Opteron6300>{{cite web | title = AMD Opteron 6300 Series processor Quick Reference Guide | url = https://www.amd.com/us/Documents/Opteron_6300_QRG.pdf | accessdateaccess-date = 2013-12-11 }}</ref>

{{Col-break}}

'''Intel Core:'''

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== Six-channel architecture ==

Supported by [[Qualcomm Centriq]] server processors,<ref>{{cite news|last1=Kennedy|first1=Patrick|title=Qualcomm Centriq 2400 ARM CPU from Hot Chips 29|url=https://www.servethehome.com/qualcomm-centriq-2400-arm-cpu-hot-chips-29/|accessdateaccess-date=14 November 2017|publisher=Serve The Home|date=23 August 2017}}</ref> and Intel Xeon Scalable processors.<ref>https://www.intel.in/content/www/in/en/products/processors/xeon/scalable/bronze-processors/bronze-3106.html</ref>

== Eight-channel architecture ==

Supported by [[AMD Epyc]] and [[Cavium#ThunderX2_SoCs|Cavium ThunderX2]] server processors.<ref>{{cite news|last1=Cutress|first1=Ian|title=AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2|url=http://www.anandtech.com/show/11183/amd-prepares-32-core-naples-cpus-for-1p-and-2p-servers-coming-in-q2|accessdateaccess-date=7 March 2017|publisher=Anandtech|date=7 March 2017}}</ref><ref>{{cite news|last1=Kennedy|first1=Patrick|title=Cavium ThunderX2 and OCP Platform Details|url=https://www.servethehome.com/cavium-thunderx2-ocp-platform-details/|accessdateaccess-date=14 November 2017|publisher=Serve the Home|date=9 November 2017}}</ref>

== See also ==