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The POWER4 chip is a computer processor based on the IBM POWER processor architecture. Released in 2001, the POWER4 chip is based on the previous POWER3 chip design, and includes compatibility with the PowerPC. The POWER4 chip is a multicore chip, including two PowerPC cores.
Functional Layout
The functional unit of the POWER4™ consists of two 64-bit implementations of the PowerPC AS Architecture. An L2 unified cache which is divided into three equal parts each having it own independent L2 controller which can feed 32 bytes of data per cycle. The Core Interface Unit (CIU) which connects each L2 controller to either the (data cache/instruction cache) in either of the two processors. A NonCacheable (NC) Unit is devoted to each processor which is responsible for handling instruction serializing functions and performing any noncacheable operations in the storage topalogy. An L3 cache controler, and the directory of the L3 (but the actual memory is off-chip). A GX bus controller which controlles I/O device communications, and two 4-byte wide GX buses one for Incoming and the other for Outgoing. A Fabric Controller which is the master controller for the network of buses, controlling communications for both L1/L2 controllers, communications between POWER4™ chips {4-way, 8-way, 16-way, 32-way} and POWER4™ MCM’s. Trace-and-Debug (used for First Failure Data Capture). A Built In Self Test function (BIST). Performance Monitoring Unit (PMU). Power-On Reset (POR).
Execution Unit
The Power4 implements a superscalar microarchitecture through high-frequency speculative out-of-order execution using 8 independent execution units. The 8 are: 2 floating-point units(FP1-2), 2 load-store units(LD1-2), 2 fixed-point units(FX1-2), 1 branch unit(BR), and 1 conditional-register unit(CR).
- Branch Prediction
- Instruction Fetch
- Decode, Crack and Group Formation
- Group Dispatch and Instruction Issue
- Load/Store Unit Operation
- Load Hit Store
- Store Hit Load
- Load Hit Load
- Instruction Execution Pipeline
Multi-Chip Configuration
Not only did the POWER4 become the first microprocessor to incorperate Dual-cores in a single die, it also concurently became the first to implement a Multi-Chip-Module(MCM) which contains four POWER4 Microprocessors in a single package.
Parametrics
| Clock GHz | >1.3 | ||
|---|---|---|---|
| Power | 115 W | 1.5 V @ 1.1 GHz | |
| Transistors | 174 million | ||
| Gate L | 90 nm | ||
| Gate oxide | 2.3 nm | ||
| Metal-layer | pitch | thickness | |
| M1 | 500 nm | 310 nm | |
| M2 | 630 nm | 310 nm | |
| M3-M5 | 630 nm | 420 nm | |
| M6(MQ) | 1260 nm | 920 nm | |
| M7(LM) | 1260 nm | 920 nm | |
| Dielectric | ~4.2 | ||
| Vdd | 1.6 V |