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Multi-core processor

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A multi-core microprocessor is one which combines two or more independent processors into a single package, often a single integrated circuit (IC). A dual-core device contains only two independent microprocessors. In general, multi-core microprocessors allow a computing device to exhibit some form of thread-level parallelism (TLP) without including multiple microprocessors in separate physical packages. This form of TLP is often known as chip-level multiprocessing, or CMP.

There is some discrepancy in the semantics by which the terms "multi-core" and "dual-core" are defined. Most commonly they are used to refer to some sort of central processing unit (CPU), but are sometimes also applied to DSPs and SoCs. Additionally, some use these terms only refer to multi-core microprocessors that are manufactured on the same integrated circuit die. These persons generally prefer to refer to separate microprocessor dies in the same package by another name, such as "multi-chip module", "double core", or even "twin core". This article uses both the terms "multi-core" and "dual-core" to reference microelectronic CPUs manufactured on the same integrated circuit, unless otherwise noted.

Conceptual diagram of a dual-core CPU, with CPU-local Level 1 caches, and shared, on-chip Level 2 caches.

Commercial examples

Development motivation

Technical pressures

While CMOS manufacturing technology continues to improve, reducing the size of single gates, physical limits of semiconductor-based microelectronics become a major design concern. Some effects of these physical limitations can cause significant heat dissipation and data synchronization problems. The demand for more complex and capable microprocessors causes CPU designers to utilize various methods of increasing performance. Some ILP methods like superscalar pipelining are suitable for many applications, but are inefficient for others that tend to contain difficult-to-predict code. Many applications are better suited to TLP methods, and multiple independent CPUs is one common method used to increase a system's overall TLP. A combination of increased available space due to refined manufacturing processes and the demand for increased TLP led to the logical creation of multi-core CPUs.

Commercial incentives

Several business motives drive the development of dual-core architectures. Since SMP designs have been long implemented using discrete CPUs, the issues regarding implementing the architecture and supporting it in software are well known. Additionally, utilizing a proven processing core design (e.g. Freescale's e700 core) without architectural changes reduces design risk significantly. Finally, the connotations of the terminology "dual-core" (and other multiples) lends itself to marketing efforts.

Additionally, for general-purpose processors, much of the motivation for multi-core processors comes from the increasing difficulty of improving processor performance by increasing the operating frequency (frequency-scaling). In order to continue delivering regular performance improvements for general-purpose processors, manufacturers such as Intel and AMD have turned to multi-core designs, sacrificing lower manufacturing costs for higher performance in some applications and systems.

It should be noted that while multi-core architectures are being developed, so are the alternatives. An especially strong contender for established markets is to integrate more peripheral functions into the chip.

Advantages

  • Proximity of multiple CPU cores on the same die have the advantage that the cache coherency circuitry can operate at a much higher clock rate than is possible if the signals have to travel off-chip, so combining equivalent CPUs on a single die significantly improves the performance of cache snoop operations.
  • Assuming that the die can fit into the package, physically, the multi-core CPU designs require much less PCB space than multi-chip SMP designs.
  • A dual-core processor uses slightly less power than two coupled single-core processors, principally because of the increased power required to drive signals external to the chip and because the smaller silicon process geometry allows the cores to operate at lower voltages.
  • In terms of competing technologies for the available silicon die area, multi-core design can make use of proven CPU core library designs and produce a product with lower risk of design error than devising a new wider core design. Also, adding more cache suffers from diminishing returns.

Disadvantages

  • Multi-core processors require operating system (OS) support to make optimal use of the second computing resource.[1] Also, making optimal use of multiprocessing in a desktop context requires application software support.
  • The higher integration of the multi-core chip drives the production yields down and are more difficult to manage thermally than lower density single-chip designs.
  • From an architectural point of view, ultimately, single CPU designs may make better use of the silicon surface area than multiprocessing cores, so a development commitment to this architecture may carry the risk of obsolescence.
  • Scaling efficiency is largely dependent on the application or problem set. For example, applications that require processing large amounts of data with low computer-overhead algorithms may find this architecture has an I/O bottleneck, underutilizing the device.

Software impact

Most existing software is not ready to directly utilize the power of multicore processors since they are written in traditional sequential programming languages like C, C++ and FORTRAN, all of which have the limited scope of only one processor in mind.

Parallel programming is a must option for a single software to exploit multiple computation units(cores) simultaneously, often by multithread or multitask programming. Some existing parallel programming models such as OpenMP and MPI can be directly used on multi-core platforms. Other research efforts have been seen also, like Cray’s Chapel, Sun’s Fortress, and IBM’s X10.

On the other hand, on the server-side multicore processors are ideal because they allow many users to connect to a site simultanesouly and have independant threads of execution. This allows for web servers and application servers that have much better throughput.

Licensing

Another issue is the question of software licensing for multi-core CPUs. Typically enterprise server software is licensed "per processor". In the past a CPU was a processor and there was no ambiguity. Now there is the possibility of counting cores as processors and charging a customer for two licenses when they use a dual-core CPU. However, the trend seems to be counting dual-core chips as a single processor as Microsoft, IBM, Intel, and AMD support this view. Oracle counts AMD and Intel dual-core CPUs as a single processor but has other funny numbers for other types. IBM and Microsoft count a multi-chip-module as multiple processors. If multi-chip-modules counted as one processor then CPU makers would have an incentive to make large expensive multi-chip-modules so their customers saved on software licensing. So it seems like the industry is slowly heading towards counting each die (see Integrated circuit) as a processor, no matter how many cores each die has. Intel has released Paxville which is really a multi-chip-module but Intel is calling it a dual-core. It is not clear yet how licensing will work for Paxville. This is an unresolved and thorny issue for software companies and customers.

Notes

  1. ^ Digital signal processors, DSPs, have utilized dual-core architectures for much longer than high-end general purpose processors. A typical example of a DSP-specific implementation would be a combination of a RISC CPU and a DSP MPU. This allows for the design of products that require a general purpose processor for user interfaces and a DSP for real-time data processing; this type of design is suited to e.g. mobile phones.
  2. ^ Two types of operating systems are able to utilize a dual-CPU multiprocessor: partitioned multiprocessing and symmetric multiprocessing (SMP). In a partitioned architecture, each CPU boots into separate segments of physical memory and operate independently; in an SMP OS, processors work in a shared space, executing threads within the OS independently.

See also

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