Template:User verilog-1

This is an old revision of this page, as edited by Hyacinth (talk | contribs) at 09:10, 19 October 2012 ({{complang|verilog|verilog}}). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.
verilog-1This user is a beginning Verilog chip designer.