Deep reactive-ion etching (DRIE) is a highly anisotropic etch process used to create deep, steep-sided holes and trenches in wafers, with aspect ratios of 20:1 or more. It was developed for microelectromechanical systems (MEMS), which require these features, but is also used to excavate trenches for high-density capacitors for DRAM.
There are two main technologies for high-rate DRIE: cryogenic and Bosch. Both Bosch and cryo processes can fabricate 90° (truly vertical) walls, but often the walls are slightly tapered, e.g. 88° or 92° ("retrograde").
Another mechanism is sidewall passivation: SiOxFy functional groups (which originate from sulphur hexafluoride and oxygen etch gases) condensate on the sidewalls, and protect them from lateral etching. As a combination of these processes deep vertical structures can be made.
Cryogenic process
In cryo-DRIE, the wafer is chilled to -110°C (163 K). The low temperature slows down the chemical reaction that produces isotropic etching. However, ions continue to bombard upward-facing surfaces and etch them away. This process produces trenches with vertical sidewalls.
Bosch process
The Bosch process, also known as pulsed or time-multiplexed etching, alternates repeatedly between two modes to achieve nearly vertical structures.
- A standard, nearly isotropic plasma etch. The plasma contains some ions, which attack the wafer from a nearly vertical direction. (For silicon, this often uses sulfur hexafluoride [SF6].)
- Deposition of a chemically inert passivation layer. (For instance, C4F8 source gas yields a substance similar to Teflon.)
Each phase lasts for several seconds. The passivation layer protects the entire substrate from further chemical attack and prevents further etching. However, during the etching phase, the directional ions that bombard the substrate attack the passivation layer at the bottom of the trench (but not along the sides). They collide with it and sputter it off, exposing the substrate to the chemical etchant.
These etch/deposit steps are repeated many times over resulting in a large number of very small isotropic etch steps taking place only at the bottom of the etched pits. To etch through a 0.5 mm silicon wafer, for example, 100-1000 etch/deposit steps are needed. The two-phase process causes the sidewalls to undulate with an amplitude of about 100-500 nm. The cycle time can be adjusted: short cycles yield smoother walls, and long cycles yield a higher etch rate.
Applications
RIE "deepness" depends on application: in DRAM memory circuits capacitor trenches may be 10-20µm deep, while in MEMS, DRIE is used for anything from a few micrometers to 0.5mm. What distinguishes DRIE from RIE is actually etch rate: while 1 µm/minute is a reasonable etch rate for RIE (as used in IC manufacturing), DRIE rates are 5-10µm/minute.
In DRIE of glass the problem is the high plasma power needed, which makes it difficult to find suitable mask materials for truly deep etching. Polysilicon and nickel are used successfully for 10-50µm etched depths. In DRIE of polymers, Bosch process with alternating steps of oxygen etching and C4F8 passivation take place. Metal masks can be used.