"Design for Test" or "Design for Testability" or "DFT": Adding special "test" circuits to chip (usually digital) for testing defects.
Most common method: "scan-design": registers are connected in a "scan chain" to gain access to internal nodes. Test patterns are shifted in via the scan chain, clock pulsed to the circuit during the "capture cycle", and the results shifted to output pins and compared against the expected results.
Scan chain can also be used to "debug" chip design by "scan dump": chip is exercised in normal mode and clocks are abruptly stopped, then configure chip in "test mode" and the logic state (1 or 0) of each register is shifted out via the scan chain. Repeated under different operating conditions by stopping the clock during different clock cycles, the internal operation of the chip can be known. This use of scan chains, along with the clock control circuits that allow the clocks to be stopped simultaneously to freeze the state of the chip is called "Design for Debug" or "Design for Debugability".