Design for Test (aka "Design for Testability" or "DFT") refers to the act of adding special "test" circuits to a chip design (usually digital) for the purpose of testing the manufactured device for defects.
The most common method for delivering test data from chip inputs to internal "circuits under test" (CUTs, for short) is called scan-design. In scan-design, registers (flip-flops or latches) in the design are connected in a "scan chain", which is used to gain access to internal nodes of the chip. Test patterns are shifted in via the scan chain, functional clock signals are pulsed to test the circuit during the "capture cycle(s)", and the results are then shifted out to chip output pins and compared against the expected "good machine" results.
In addition to being useful for manufacturing "go/no go" testing, scan chains can also used to "debug" chip designs. In this context, called "scan dump" mode, the chip is exercised in normal "functional mode" (for example, a computer or mobile-phone chip might execute assembly language instructions), and the clocks are abruptly stopped. The chip is then configured in "test mode" and the state of the chip -- that is, the logic state (1 or 0) of each register -- is shifted out via the scan chain(s). If repeated under different operating conditions and by stopping the clock during different tadjacent) clock cycles, a debug engineer can learn much about the internal operation of the chip and pass that information along to chip designers, who might tweak the design to fix the bug, or -- if the device passes at slower clock frequencies but fails at higher frequencies -- to add more timing margin. This use of scan chains, along with the clock control circuits that allow the clocks to be stopped simultaneously to freeze the state of the chip -- are a related sub-discipline of logic design called "Design for Debug" or "Design for Debugability".