Application-specific instruction set processor

An application-specific instruction-set processor (ASIP) is a component used in system-on-a-chip design. The instruction set of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose CPU and the performance of an ASIC.

Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: static logic which defines a minimum ISA and configurable logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to an FPGA or during the chip synthesis.

Literature

• Oliver Schliebusch, Heinrich Meyr, Rainer Leupers (2007). Optimized ASIP Synthesis from Architecture Description Language Models. Dordrecht: Springer. ISBN 978-1-4020-5685-7.
• Paolo Ienne, Rainer Leupers (eds.) (2006). Customizable Embedded Processors. San Mateo, CA: Morgan Kaufmann. ISBN 978-0-12-369526-0. {{cite book}}: |author= has generic name (help)
• Matthias Gries, Kurt Keutzer (eds.) (2005). Building ASIPs: The Mescal Methodology. New York: Springer. ISBN 978-0-387-26057-0. {{cite book}}: |author= has generic name (help)

Increasing Design Costs

    Designing an integrated circuit is getting increasingly expensive with 

each succeeding generation. Design difficulties arise from four distinct causes:

Deep-Submicron Effects (DSM):

    The primary change is the increase in interconnect delay as a fraction of 
    the gate delay due to scaling effects. Since this is not available till
physical design is over, the traditional synthesis flow of logic 

synthesis, with simple interconnect wire-load models, followed by physical synthesis does not work anymore.

Increased Complexity: The flip-side of smaller geometries is that we can

    now integrate more transistors on the same die. This is
amplified by the fact that manufacturing advances have further 
increased possible die-sizes. 

Heterogeneous Integration: Increased functionality of systems

at lower costs requires the integration of heterogeneous
functionality on the same die. In addition to the traditional
digital part, it is not uncommon to integrate analog and mixed 

signal components on the same die.

Shrinking Time-to-Market: :

While the above three factors arise 

out of technology challenges, the fourth arises

from commercial challenges. Increasingly, the time-to-market
for products is shrinking – providing the added degree of 

difficulty in realizing commercially successful designs.

Increasing Manufacturing Costs

    Mask costs for designs in today’s 180-130nm 

technologies are in the 0.5-1M$ range.

    Testing 100M-1B transistor circuits 

at high operating frequencies poses significant challenges.

    ITRS 2001 states that “test costs have 

grown exponentially compared to manufacturing costs".