Adaptive voltage scaling

Adaptive Voltage Scaling (AVS) is a closed-loop dynamic power minimization technique which reduces power based on the actual operating conditions of a computer chip. Many computer chips, especially those in mobile devices or Internet of things devices are constrained by the power available (for example, they are limited to the power stored in a battery) and face varying workloads.^[1] In addition, individual chips can vary in their efficiency due to minor differences in manufacturing conditions.^[2] AVS allows the voltage supplied to the chip, and therefore its power consumption, to be continuously adjusted to be appropriate to the workload. This is accomplished by integrating a device that monitors the performance of the chip (a hardware performance manager) into the chip, which then provides information to a power controller.^[3] The reduction in power also reduces the heat generated by the chip.

AVS is similar in its goal to Dynamic Voltage Scaling (DVS) and Dynamic Voltage and Frequency Scaling (DVFS). All three approaches aim to reduce power usage.^[4] However AVS adapts the voltage directly to the conditions on the chip,^[5] allowing it to address chip-to-chip variations and changes in performance that occur as the chip ages.

Dynamic Approaches to reduce power in digital circuits

Background

Technological advances have enabled very powerful and versatile computing systems to be implemented on smaller chips. As this allows a larger number of functions to take place in the same area, both current density and the associated power dissipation become more concentrated compared to larger chips. The power consumption and thermal performance of integrated circuits has become a limiting factor for high-performance systems.^[6][7][8] Mobile devices are also limited by the total amount of power available.^[5] Minimizing power consumption in digital CMOS circuits requires significant design effort at all levels. Supply Voltage reduction is one technique to achieve this, but static supply voltage reduction can cause performance degradation. Dynamic voltage scaling systems are used to adjust the supply voltage to the specific operations the chip is performing. However, conventional DVS systems do not directly monitor the performance of individual sectors of the chip and must therefore be adjusted to accommodate operation under worst-case performance scenarios.^[5] AVS aims to supply each individual ___domain of the system on the chip with just enough voltage to perform its task under the conditions actually experienced by the chip, minimizing power consumption per processor ___domain.^[9]

Overview

Adaptive voltage scaling is a closed-loop Dynamic Voltage Scaling approach that considers different factors, such as process variations from device to device on a chip, temperature fluctuations during chip operations, and load variations, and establishes a voltage-frequency relation for the reduction in power dissipation of the circuit under those conditions. Each individual chip's process corner is determined either during manufacturing or during runtime and the optimal voltage-frequency relationship is determined and subsequently used for voltage optimization. The features offered by this approach are:^[4][9]

• Delivery of the desired voltage to every block of the system even across temperature, process corner and frequency variations.
• Processor- and architecture-independent implementation of power reduction.
• Typical savings of about 55% over the open-loop Dynamic Voltage Scaling approaches^{[citation needed]}.

Adaptive voltage scaling is used to address the energy-saving requirements of application-specific integrated circuits, microprocessors and system on a chip circuits. It is also well-suited for high-volume systems such as data centers and wireless base stations, as well as for the power-constrained applications such as portable devices, USB peripherals, and consumer electronics.^[9]

Comparison Between the Open-Loop DVS Technique and AVS

The architecture of the generic Dynamic Voltage Scaling system has a performance manager, a Phase-locked loop and a Voltage regulator.^[10] The performance manager block uses a software interface in order to predict the performance requirements of the next task. Once the determination of the power requirement is done, the voltage and frequency are set by the performance manager in order to finish the task. The phase-locked loop accomplishes the frequency scaling depending on the target frequency set by the performance manager. Similarly, the voltage regulator is programmed to scale the supply voltage in order to achieve the target voltage for the task. Thus, the characterization of the systems employing DVS requires characterization of at least two ends of its operating range. In fact, the characterization of DVS systems depends on the underlying voltage scaling methodology. The basic operation of both open-loop DVS systems (the conventional DVS systems) and the closed-loop DVS systems (Adaptive Voltage Systems) is only different in the selection of the target voltage-frequency relationship. The open-loop DVS systems employ the one-to-one mapping of the voltage to frequency to perform the voltage scaling. The frequency-voltage pairs are stored in a lookup table and are obtained as per the determined task needs. The frequency-voltage relationship is determined by considering the chip characterization at worst-case conditions so as to guarantee a robust operation under those conditions. In order to accommodate the worst-case conditions, there is a significant power margin left by the open-loop DVS systems for power scaling. This margin is not lost in closed-loop systems because they employ a feedback mechanism that keeps probing the actual on-chip conditions and determining the target voltage and frequency from these conditions.^[8][9] Open-loop systems guarantee temperature stability but because of this, do not reduce power consumption as much as closed-loop systems.

Implementation of a Circuit That Monitors On-Chip Variations in AVS Systems

The closed-loop voltage scaling system utilizes on-chip circuit structures to provide feedback that is required to adaptively track the actual silicon behavior. One commonly used approach is to use a ring oscillator that operates at the same voltage as that of the rest of the chip. The voltage-frequency relationship for the chip at that particular frequency is determined by the frequency of the ring oscillator.

Critical Path Monitoring Techniques

 

Critical Path Monitoring Technique for Adaptive Voltage Scaling

The voltage-frequency relationship for the chip can also be determined by using another approach which tries to model the critical path of the chip. The critical path of the system can be duplicated using a ring oscillator or by a fan out of four Ring oscillator^[8] or a delay line. This critical path replica (delay line) provides the closest behavior to the actual critical path except for the intra-die variations and cross-coupling capacitances which are hard to duplicate. This delay line adapts to environmental and process variations. Since the actual performance of the core and the speed of the delay line are directly related, a closed-loop Adaptive Voltage Scaling system is obtained to automatically adjust the supply voltage such that the minimum voltage is supplied for the target task.^[5]

The delay chain consists of inverters, NAND gates, wire segments, etc., and the output can be tapped from one of the points, thus allowing tuning of the delay to match a chip's critical path. A reconfigurable delay chain can also be used in the critical path monitoring technique. The exact setting of the delay chain is determined during the manufacturing test. In order to measure the delay during AVS operation, a rising edge is launched at the start of the clock cycle, then captured at the end of the clock cycle at the output of delay chain, along with a set of buffers.^{[clarification needed]} Then the buffer outputs that are captured are analyzed to determine the exact positioning of the rising edge. Now the feedback employed by the AVS system continually adjusts the supply voltage such that the delay chain and critical path meet the timing constraints with adequate margins. The adjustment of the supply voltage is done such that the launched rising edge reaches a specified buffer stage which ensures the timing of the delay line.^[8][11][12]

Challenges in Critical Path Monitoring Techniques

Sufficient safety margins can be included in order to account for any mismatch between the delay line(critical path monitor) and the actual critical path in order to account for the inevitable large within-die process variations. These large variations can cause the critical path to change from one process corner to another. Thus, in order to maintain a fail-safe operation, an additional delay margin should be maintained. This margin is translated into a voltage overhead that directly reduces the energy savings from the AVS approach.^[11] The process and temperature variations of the closed-loop systems are compensated by continuously monitoring the activity of a critical path replica. In the sub-micrometer technologies, the use of a single reference in the critical path is less feasible because the selection of a unique critical path across all conditions becomes very challenging. This is because of increased variation of transistors and wires within the node. Also, when the contribution of interconnect delay increases, there might be several paths that have different combinations of logic and interconnect delay, with their overall delays being close to each other. In that case, the selection of the critical path becomes even more challenging.^[8]

Razor Approach

The bottlenecks of the critical path approach can be avoided by implementing the razor approach, which identifies more than one potential critical path.^[8] In this approach, an on-chip timing checker is employed to check the timing margin of the critical path. A delayed version of the system clock is used by the timing circuit to capture the data in shadow latch which is same as the data captured by the master (main) flip-flop. Wherever the sub-paths become critical, additional shadow latches are introduced. When the supply voltage is scaled, the value latched in the main flip-flop might be different from that of those latched by the shadow latches, which results in error signals. The error signals from all the shadow latches are gathered to generate a single error indicator. This error is corrected by flushing the pipeline and reloading the state that was existing before the error occurred. When the error rates decrease beyond certain limits the supply voltage is reduced until the point where the error tends to become unacceptable.^[5][8]

Challenges in Razor Approach

• In order to guarantee the robust operation of the system, characterization at all conditions must be known, which requires an increased number of latches. This increases the probability of error, as well as the overhead of the error detection circuit.
• When the error rate increases the latency which arises due to flushing of the pipeline might negatively affect the overall system performance.
• When the design has many critical paths which are close to each other in timing, then more shadow latches are needed resulting in increased overhead and reduced efficiency. This increases the complexity of the razor approach.

Issues Related to Bias Temperature Instability

Bias temperature instability (BTI), an aging [sic?] mechanism in CMOS technology causes time-dependent degradation in VLSI circuits. Adaptive voltage scaling can be used to mitigate the BTI-induced timing degradation by increasing the supply voltage dynamically. This can be achieved as long as the BTI degradation is captured by the performance sensor in the AVS system. However, the use of AVS during the lifetime of the chip poses new challenges for the margin reduction in the sign-off methodology which characterizes the timing libraries based on the transistor models with the pre-calculated BTI degradation for given integrated circuit lifetime.^[12]

See also

• Power Dissipation
• Low Power Electronics
• Dynamic Voltage scaling
• Bias Temperature Instability

References

1. Keller, B.; Cochet, M.; Zimmer, B.; Lee, Y.; Blagojevic, M.; Kwak, J.; Puggelli, A.; Bailey, S.; Chiu, P. (2016). "Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC" (PDF). ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference: 269–272. doi:10.1109/ESSCIRC.2016.7598294.
2. Horowitz, M.; Alon, E.; Patil, D.; Naffziger, S.; Rajesh Kumar; Bernstein, K. (2005). "Scaling, power, and the future of CMOS" (PDF). IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.: 7 pp.–15. doi:10.1109/IEDM.2005.1609253.
3. Kushwaha, Sunita; Kumar, Sanjay (2016). "Energy Saving Approaches for Scheduling on Parallel Systems - A Review" (PDF). International Journal of Computer Applications. 152: 38–42.
4. Texas Instruments Application Report,"Adaptive (Dynamic) voltage (Frequency) scaling - Motivation and implementation"
5. Gupte, Ajit; Dwivedi, Satyam; Mehta, Nandish; Amrutur, Bharadwaj (2011). "Adaptative Techniques to Reduce Power in Digital Circuits". Journal of Low Power Electronics and Applications. 1 (2): 261–276. doi:10.3390/jlpea1020261.
6. Nakai, M.; Akui, S.; Seno, K.; Meguro, T.; Seki, T.; Kondo, T.; Hashiguchi, A.; Kawahara, H.; Kumano, K. (2005). "Dynamic voltage and frequency management for a low-power embedded microprocessor". IEEE Journal of Solid-State Circuits. 40 (1): 28–35. doi:10.1109/JSSC.2004.838021. ISSN 0018-9200.
7. Rabaey,J.Low Power Design Essentials, springer :New York ,NY,USA,2009.
8. Elgebaly, M.; Sachdev, M. (2007). "Variation-Aware Adaptive Voltage Scaling System". IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 15 (5): 560–571. doi:10.1109/TVLSI.2007.896909. ISSN 1063-8210.
9. National Products from Texas Instruments, “Adaptive voltage scaling technology, up to 60% energy savings on core operation”
10. Mohamed Eglebaly, Manoj Sachdev . "Variation Aware Adaptive Voltage Scaling system".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,VOL.15,NO.5,MAY 2007.
11. Bharadwaj Amrutur , Nandish Mehta , satyam Dwivedi, Ajit Gupte . "Adaptive techniques to reduce power in digital circuits".Journal of low power electronics and applications , 4 July 2011.
12. Tuck-Boon Chan, wei-Ting Jonas Chan and Andrew B.Kahng."Impact of Adaptive Voltage Scaling on Aging-Aware Sign off".IEEE Design Automation and Test in Europe conference & Exhibition ,2013. DOI 10.7873