The MCS-48 microcontroller series, Intel's first microcontroller, was originally released in 1976. Its first members were 8048, 8035 and 8748. The 8048[1] is arguably the most prominent member of the family. Initially, this family was produced using NMOS (n-type metal–oxide–semiconductor) technology. In the early 1980s, it became available in CMOS technology. It was manufactured into the 1990s to support older designs that still used it.
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The MCS-48 series has a modified Harvard architecture, with internal or external program ROM and 64 to 256 bytes of internal (on-chip) RAM. The I/O is mapped into its own address space, separate from programs and data.
Though the MCS-48 series was eventually replaced by the very successful MCS-51 series, it remained quite popular even by the year 2000 due to its low cost, wide availability, memory-efficient one-byte instruction set, and mature development tools. Because of this, it is used in high-volume, cost-sensitive consumer electronics devices such as TV remotes, computer keyboards, and toys.
Variants
editThe 8049 has 2 KB of masked ROM (the 8748 and 8749 had EPROM) that can be replaced with a 4 KB external ROM, as well as 128 bytes of RAM and 27 I/O ports.[2] The microcontroller's oscillator block divides the clock input frequency by three and then further divides the result into five machine states. Using the 11 MHz maximum crystal frequency will produce 0.73 MIPS of single-cycle instructions. Some 70% of instructions are single byte and single cycle ones, but 30% need two cycles or two bytes, so its typical performance would be closer to 0.5 MIPS.
| Device | Internal | Memory | Remarks |
|---|---|---|---|
| 8020 | 1K × 8 ROM | 64 × 8 RAM | subset of 8048, 20 pins, only 13 I/O lines |
| 8021 | 1K × 8 ROM | 64 × 8 RAM | subset of 8048, 28 pins, 21 I/O lines |
| 8022 | 2K × 8 ROM | 64 × 8 RAM | subset of 8048, A/D-converter |
| 8035 | none | 64 × 8 RAM | |
| 8038 | none | 64 × 8 RAM | |
| 8039 | none | 128 × 8 RAM | |
| 8040 | none | 256 × 8 RAM | |
| 8048 | 1K × 8 ROM | 64 × 8 RAM | 27× I/O ports |
| 8049 | 2K × 8 ROM | 128 × 8 RAM | 27× I/O ports |
| 8050 | 4K x 8 ROM | 256 × 8 RAM | |
| 8648 | 1K × 8 OTP EPROM | 64 × 8 RAM | Factory OTP EPROM |
| 8748 | 1K × 8 EPROM[3] | 64 × 8 RAM[3] | 4K program memory expandable,[3] 2× 8-bit timers, 27× I/O ports |
| 8749 | 2K × 8 EPROM | 128 × 8 RAM | 2× 8-bit timers, 27× I/O ports |
| 87P50 | ext. ROM socket | 256 × 8 RAM | Has piggy-back socket for 2758/2716/2732 EPROM |
| Device | Internal | Memory | Remarks |
|---|---|---|---|
| 8041 | 1K × 8 ROM | 64 × 8 RAM | Universal Peripheral Interface (UPI) |
| 8041AH | 1K × 8 ROM | 128 × 8 RAM | UPI |
| 8741A | 1K × 8 EPROM | 64 × 8 RAM | UPI, EPROM version of 8041 |
| 8741AH | 1K × 8 OTP EPROM | 128 × 8 RAM | UPI, OTP EPROM version of 8041AH |
| 8042AH | 2K × 8 ROM | 256 × 8 RAM | UPI |
| 8242 | 2K × 8 ROM | 256 × 8 RAM | UPI, preprogrammed with keyboard controller firmware[4] |
| 8742 | 2K × 8 EPROM | 128 × 8 RAM | UPI, EPROM version |
| 8742AH | 2K × 8 OTP EPROM | 256 × 8 RAM | UPI, OTP EPROM version of 8042AH |
Uses
editThe MCS-48 series was commonly used in computer and terminal keyboards, converting key presses into protocols that can be understood by digital circuits. This also allows the possibility of serial communication, reducing the number of conductors needed in cables on external keyboards. Microprocessors had been used in keyboards since at least 1972, simplifying earlier discrete designs. The 8048 has been used in this application since its introduction in 1978.[citation needed]
The Tandy/Radio Shack TRS-80 Model II, released in 1979, used the 8021 in its keyboard.[5] The 8021 processor scans the key matrix, converts switch closures to an 8-bit code and then transmits that code serially to the keyboard interface on the main system. It will also accept commands to turn indicator LEDs on or off. The 8021 was also used in the keyboards for the TRS-80 Model 12, 12B, 16, 16B and the Tandy 6000/6000HD.[6]
The original IBM PC keyboard used an 8048 as its internal microcontroller.[7] The PC AT replaced the PC's Intel 8255 peripheral interface chip at I/O port addresses 0x60–63 with an 8042 accessible through port addresses 0x60 and 0x64.[8] As well as managing the keyboard interface, the 8042 controlled the A20 line gating function for the AT's Intel 80286 CPU and could be commanded by software to reset the 80286 (unlike the 80386 and later processors, the 80286 had no way of switching from protected mode back to real mode except by being reset). Later PC compatibles integrate the 8042's functions into their super I/O devices.
The 8048 was used in the Magnavox Odyssey² video game console, the Korg Trident series,[9] and the Korg Poly-61,[10] Roland Jupiter-4 and Roland ProMars[11] analog synthesizers. The Sinclair QL used the closely related Intel 8049 to manage its keyboard, joystick ports, RS-232 inputs and audio. The ROM-less 8035 variant was used in Nintendo's arcade game Donkey Kong to generate the background music.
Instruction set
editAll MCS-48 instructions are one or two bytes long with 70% of the instructions being one byte. The MCS-48 can address 4096 bytes of program memory, 256 bytes of RAM, and eight port I/O addresses. Most arithmetic and logical operations use the accumulator as a parameter and destination. Eight memory locations are mapped as registers so they can be addressed by a 3-bit field embedded in many instructions. Two of those registers can be used as memory pointers. Conditional branches can only access the current 256-byte page. JMP and CALL can directly access 2048 locations. To access the entire 4096 byte program space, a clunky select memory bank instruction must be used. The RET instruction can, however, return anywhere in the address space. Interrupts are well supported with alternate registers for quick context switches and the ability to restore the state of the flags with the RETR instruction. All instructions execute in one or two machine cycles. Each machine cycle takes 15 external clocks.
| Opcode | Operand | Mnemonic | Cycles | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | — | NOP | 1 | No operation |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | — | OUTL BUS,A | 2 | Bus latch ← A |
| ALUI | 0 | 0 | 1 | 1 | data | ADD ADDC MOV ORL ANL XRL | 2 | A ← A ALU # | |||
| addhi | 0 | 0 | 1 | 0 | 0 | addlo | JMP add | 2 | PC ← DBF:addhi:addlo | ||
| 0 | 0 | 0 | I | 0 | 1 | 0 | 1 | — | EN/DIS I | 1 | I ← 0 (EN) or I ← 1 (DIS) |
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | — | DEC A | 1 | A ← A - 1 |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | — | INS A,BUS | 2 | A ← bus |
| 0 | 0 | 0 | 0 | 1 | 0 | PP | — | IN A,Pp | 2 | A ← Port(p) (Ports 1-2) | |
| 0 | 0 | 0 | 0 | 1 | PP | — | MOVD A,Pp | 2 | A0-3 ← 8243 Port(p); A4-7 ← 0 (Ports 4-7) | ||
| ALU | 0 | 0 | 0 | R | — | INC XCH ORL ANL ADD ADDC MOVRA XRL MOVAR |
1 | dest ← dest ALU @Rr (@R0, @R1 only; no DEC) | |||
| ALU | 1 | RRR | — | INC XCH ORL ANL ADD ADDC MOVRA DEC XRL MOVAR |
1 | dest ← dest ALU Rr | |||||
| BIT | 1 | 0 | 0 | 1 | 0 | addr | JBb addr | 2 | If A ∧ (1 << b) then PC0-7 ← addr | ||
| addhi | 1 | 0 | 1 | 0 | 0 | addlo | CALL add | 2 | (SP) ← PSW4-7:PC; SP ← SP + 1; PC ← DBF:addhi:addlo | ||
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | addr | JTF addr | 2 | If TF = 1 then PC0-7 ← addr (timer flag set) |
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | — | INC A | 1 | A ← A + 1 |
| 0 | 0 | 1 | T | 0 | 1 | 0 | 1 | — | EN/DIS TCNTI | 1 | TCNTI ← 0 (EN) or TCNTI ← 1 (DIS) (timer/counter interrupt) |
| 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | addr | JNT0 addr | 2 | If T0 = 0 then PC0-7 ← addr (test 0 low) |
| 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | — | CLR A | 1 | A ← 0 |
| 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | addr | JT0 addr | 2 | If T0 = 1 then PC0-7 ← addr (test 0 high) |
| 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | — | CPL A | 1 | A ← ¬A |
| 0 | 0 | 1 | 1 | 1 | 0 | PP | — | OUTL Pp,A | 2 | Port(p) ← A (Ports 1-2) | |
| 0 | 0 | 1 | 1 | 1 | PP | — | MOVD Pp,A | 2 | 8243 Port(p) ← A0-3 (Ports 4-7) | ||
| 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | — | MOV A,T | 1 | A ← T (Move timer to A) |
| 0 | 1 | 0 | T | 0 | 1 | 0 | 1 | — | STRT CNT/T | 1 | If T = 0 start count else start timer |
| 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | addr | JNT1 addr | 2 | If T1 = 0 then PC0-7 ← addr (test 1 low) |
| 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | — | SWAP A | 1 | A0-3 ↔ A4-7 |
| 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | addr | JT1 addr | 2 | If T1 = 1 then PC0-7 ← addr (test 1 high) |
| 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | — | DA A | 1 | If A0-4 > 9 OR AC = 1 then A ← A + 6;
then if A4-7 > 9 OR C = 1 then A ← A + 0x60 |
| 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | — | MOV T,A | 1 | T ← A (Move A to timer) |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | — | STOP TCNT | 1 | Stop timer and count |
| 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | — | RRC A | 1 | C ← A0; A0-6 ← A1-7; A7 ← C |
| 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | — | ENT0 CLK | 1 | Set T0 as a clock output |
| 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | addr | JF1 addr | 2 | If F1 = 1 then PC0-7 ← addr |
| 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | — | RR A | 1 | A0-6 ← A1-7; A7 ← A0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | — | RET | 2 | SP ← SP - 1; PC ← (SP) |
| 1 | 0 | N | 0 | 0 | 1 | 0 | 1 | — | CLR Fn | 1 | Fn ← 0 |
| 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | addr | JNI addr | 2 | If I input = 0 then PC0-7 ← addr (test interrupt input low) |
| 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | data | ORL BUS,# | 2 | A ← bus ∨ # |
| 1 | 0 | 0 | 0 | 1 | 0 | PP | data | ORL Pp,# | 2 | A ← Port(p) ∨ # (Ports 1-2) | |
| 1 | 0 | 0 | 0 | 1 | PP | — | ORLD Pp,A | 2 | 8243 Port(p) ← 8243 Port(p) ∨ A0-3 (Ports 4-7) | ||
| 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | — | RETR | 2 | SP ← SP - 1; PC ← (SP); PSW4-7 ← (SP) |
| 1 | 0 | N | 1 | 0 | 1 | 0 | 1 | — | CPL Fn | 1 | Fn ← ¬Fn |
| 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | — | CLR C | 1 | C ← 0 |
| 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | data | ANL BUS,# | 2 | A ← bus ∧ # |
| 1 | 0 | 0 | 1 | 1 | 0 | PP | data | ANL Pp,# | 2 | A ← Port(p) ∧ # (Ports 1-2) | |
| 1 | 0 | 0 | 1 | 1 | PP | — | ANLD Pp,A | 2 | 8243 Port(p) ← 8243 Port(p) ∧ A0-3 (Ports 4-7) | ||
| 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | — | MOVP A,@A | 2 | A ← (PC8-11:A) (read program memory) |
| 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | — | CPL C | 1 | C ← ¬C |
| 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | — | JMPP @A | 2 | PC0-7 ← A (indirect JMP) |
| 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | addr | JF0 addr | 2 | If F0 = 1 then PC0-7 ← addr |
| 1 | 1 | N | 0 | 0 | 1 | 0 | 1 | — | SEL RBn | 1 | BS ← n (select register bank) |
| 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | addr | JZ addr | 2 | If A = 0 then PC0-7 ← addr |
| 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | — | MOV A,PSW | 1 | A ← PSW |
| 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | — | MOV PSW,A | 1 | PSW ← A |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | — | MOVP3 A,@A | 2 | A ← (PC ← 0011:A) (read page 3 program memory) |
| 1 | 1 | 1 | N | 0 | 1 | 0 | 1 | — | SEL MBn | 1 | DBF ← n (select memory bank: PC11) |
| 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | addr | JNC addr | 2 | If C = 0 then PC0-7 ← addr |
| 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | — | RL A | 1 | A1-7 ← A0-6; A0 ← A7 |
| 1 | 1 | 1 | 0 | 1 | RRR | addr | DJNZ Rr,addr | 2 | Rr ← Rr - 1; If Rr ≠ 0 then PC0-7 ← addr | ||
| 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | addr | JC addr | 2 | If C = 1 then PC0-7 ← addr |
| 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | — | RLC A | 1 | C ← A7; A1-7 ← A0-6; A0 ← C |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Operand | Mnemonic | Cycles | Description |
| RRR or R | 3 | 2 | 1 | 0 | ALU | ALUI #immed | |||||
| R0 @R0 | 0 | 0 | 0 | 0 | ADD A,# (A ← A + #) | ||||||
| R1 @R1 | 0 | 0 | 0 | 1 | INC arg (arg ← arg + 1) | ADDC A,# (A ← A + # + C) | |||||
| R2 | 0 | 0 | 1 | 0 | XCH A,arg (A ↔ arg) | MOV R,# (R ← #) | |||||
| R3 | 0 | 0 | 1 | 1 | |||||||
| R4 | 0 | 1 | 0 | 0 | ORL A,arg (A ← A ∨ arg) | ORL A,# (A ← A ∨ #) | |||||
| R5 | 0 | 1 | 0 | 1 | ANL A,arg (A ← A ∧ arg) | ANL A,# (A ← A ∧ #) | |||||
| R6 | 0 | 1 | 1 | 0 | ADD A,arg (A ← A + arg) | ||||||
| R7 | 0 | 1 | 1 | 1 | ADDC A,arg (A ← A + arg + C) | ||||||
| 1 | 0 | 1 | 0 | MOV R,A (R ← A) | |||||||
| 1 | 1 | 0 | 0 | DEC arg (arg ← arg - 1) | |||||||
| 1 | 1 | 0 | 1 | XRL A,arg (A ← A ⊻ arg) | XRL A,# (A ← A ⊻ #) | ||||||
| 0 | 1 | 1 | 1 | MOV A,R (A ← R) | |||||||
| RRR or R | 3 | 2 | 1 | 0 | ALU | ALUI #immed | |||||
Derived microcontrollers
editPhilips Semiconductors (now NXP) owned a license to produce this series and developed their MAB8400-family based on this architecture. These were the first microcontrollers with an integrated I²C-interface and were used in the first Philips (Magnavox in the US) Compact Disc players (e.g. the CD-100).[12]
- Intel MCS-48 second sources
-
Mitsubishi Electric M5M80C39P-6 -
Fujitsu MBL8742H -
Kvazar Kiev KM1816VE48 (Soviet Union – 8748 clone) -
National Semiconductor NS87PC48D (piggyback variant) -
Signetics SCN8048A -
-
Philips MAF 8049H
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See also
editReferences
edit- ^ Laws, David; Blume Jr., Henry; Ekiss, John; Feng, Yung; Kline, Barbara; Raphael, Howard; Stamm, David (2008-07-30). Oral History Panel on the Development and Promotion of the Intel 8048 Microcontroller (PDF). Archived from the original (PDF) on 2014-12-27.
- ^ Intel Corporation 1978.
- ^ a b c Hayes, John P. (1978). Computer Architecture and Organization. McGraw-Hill International Book Company. pp. 57–59. ISBN 0-07-027363-4.
- ^ "UPI-41AH/42AH Universal Peripheral Interface 8-bit Slave Microcontroller" (PDF). Intel. November 1994. p. 2. Retrieved 2022-07-19.
- ^ TRS-80 Model II Technical Reference Manual. Radio Shack. p. 135.
- ^ Tandy 6000/6000HD Service Manual. Tandy/Radio Shack. 1985. p. 213.
- ^ "Section 4: Keyboard", Technical Reference: Personal Computer, Personal Computer Hardware Reference Library (Revised ed.), IBM, April 1984
- ^ "Section 1: System Board", Technical Reference: Personal Computer AT, Personal Computer Hardware Reference Library, IBM, September 1985
- ^ "Korg Trident Service Manual". Korg. p. 4. Retrieved 10 February 2018 – via Synthfool.
- ^ "Korg Poly-61 Service Manual" (PDF). Archived from the original (PDF) on 2010-06-02. Retrieved 2013-03-07.
- ^ Gordon Reid (November 2004). "The History Of Roland, Part 1: 1930–1978". The History Of Roland. Sound On Sound Magazine. Retrieved 29 November 2010.
- ^ Datasheet (pdf) Philips MAB8400-Family
Bibliography
edit- MCS-48
- MCS-48 Single Component Microcomputer (Applications Seminar Notebook). Intel Corporation. 1978.
- MCS-48 Microcomputer User's Manual (PDF). Intel Corporation. 1978.
- Smith, Lionel; Moore, Cecil (January 1979). "Serial I/O and Math Utilities for the 8049 Microcomputer". Intel Corporation. Application Note AP-49.
- A High-Speed Emulator for Intel MCS-48 Microcomputers. Intel Corporation. August 1979. Application Note AP-55A.
- Dahm, Phil; Rosenberg, Stuart (December 1979). Intel MCS-48 and UPI-41A Microcontrollers. Intel Corporation. Reliability Report RR-25.
- Microcontroller Handbook (PDF). Intel. 1984. Order number 210918-002.
- 8-Bit Embedded Controllers (PDF). Intel. 1991. Order number 270645-003.
- UPI-41
- Intel (1980). UPI-41A User's Manual (PDF). Order number 9800504-02 Rev. B.
- Microprocessor Peripherals UPI-41A/41AH/42/42AH User's Manual (PDF). Intel Corporation. October 1993. 231318-006.
- Beaston, Johan; Kahn, Jim (May 1980). An 8741A/8041A Digital Cassette Controller. Intel Corporation. Application Note AP-90.