Revision as of 07:19, 12 August 2025 edit Lkcl (talk \| contribs) Extended confirmed users 3,004 edits →Intel and AMD (x86): link to GFNI subset Tags: Mobile edit Mobile web edit Advanced mobile edit ← Previous edit		Revision as of 07:19, 12 August 2025 edit undo Lkcl (talk \| contribs) Extended confirmed users 3,004 edits →Intel and AMD (x86) Tags: Mobile edit Mobile web edit Advanced mobile edit Next edit →
Line 30: ** Bit extract/bit deposit {{code\|pext}}/{{code\|pdep}} * The [[AVX-512#Bitwise ternary logic\|AVX-512 ternary]] extension includes a [[Bitwise ternary logic instruction]], {{code\|vpternlog}}. Also noteworthy is a conflict detection instruction. [[AVX-512#Conflict detection\|<code>VPCONFLICTD</code>]] * Also present in the AVX/[[AVX-512]] [[~~GNFI~~GFNI instruction set\|GFNI subset]] is bit-matrix affine transformation and its inverse: {{code\|GF2P8AFFINEQB}} is effectively an 8x8 bit-matrix multiply in the [[Galois field]] GF(2^8).<ref>{{cite web \| title=GF2P8AFFINEQB — Galois Field Affine Transformation \| url=https://www.felixcloutier.com/x86/gf2p8affineqb }}</ref> * An Intel GNFI technology guide on that AVX/AVX512 GNFI Extension also lists numerous uses including parallel byte-wise set/clear/invert bitmanipulation, 5-bit sign-extension and points out the potential is much greater.<ref name=gfni>{{cite web \|title=Galois Field New Instructions (GFNI) Technology Guide \|url=https://networkbuilders.intel.com/solutionslibrary/galois-field-new-instructions-gfni-technology-guide \|website=networkbuilders.intel.com \|language=en}}</ref> * [[Intel BCD opcodes]]

Bit manipulation instructions: Difference between revisions