Soft microprocessor: Difference between revisions

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{{Short description|microprocessorMicroprocessor design embeddable in other computer systems}}

{{Use American English|date = April 2019}}

{{missing information||three [[OpenPOWER]] cores, one Moxie core, both at RTL level|date=July 2020}}

A '''soft microprocessor''' (also called softcore microprocessor or a '''soft processor''') is a [[microprocessor]] core that can be wholly implemented using [[logic synthesis]]. It can be implemented via different [[semiconductor]] devices containing programmable logic (e.g., [[Application-specific integrated circuit|ASIC]], [[Field-programmable gate array|FPGA]], [[Complex programmable logic device|CPLD]]), including both high-end and commodity variations.<ref>http://www.dailycircuitry.com/2011/10/zet-soft-core-running-windows-30.html {{Webarchiveusurped|url1=[https://web.archive.org/web/20181013095941/http://www.dailycircuitry.com/2011/10/zet-soft-core-running-windows-30.html |date=2018-10-13Article title]}}

{{Short description|microprocessor design embeddable in other computer systems}}

A '''soft microprocessor''' (also called softcore microprocessor or a '''soft processor''') is a [[microprocessor]] core that can be wholly implemented using [[logic synthesis]]. It can be implemented via different [[semiconductor]] devices containing programmable logic (e.g., [[Application-specific integrated circuit|ASIC]], [[Field-programmable gate array|FPGA]], [[Complex programmable logic device|CPLD]]), including both high-end and commodity variations.<ref>http://www.dailycircuitry.com/2011/10/zet-soft-core-running-windows-30.html {{Webarchive|url=https://web.archive.org/web/20181013095941/http://www.dailycircuitry.com/2011/10/zet-soft-core-running-windows-30.html |date=2018-10-13 }}

"Zet soft core running Windows 3.0" by Andrew Felch 2011</ref>

Most systems, if they use a soft processor at all, only use a single soft processor. However, a few designers tile as many soft cores onto an FPGA as will fit.<ref>

{{cite web |url=http://www.embedded.com/columns/showArticle.jhtml?articleID=192700615 |title=ArchivedEmbedded.com copy- FPGA Architectures from 'A' to 'Z' : Part 2 |access-date=2012-08-18 |url-status=dead |archive-url=https://web.archive.org/web/20071008163016/http://www.embedded.com/columns/showArticle.jhtml?articleID=192700615 |archive-date=2007-10-08 }}

"FPGA Architectures from 'A' to 'Z'" by Clive Maxfield 2006

</ref> In those [[multi-core]] systems, rarely used resources can be shared between all the cores in a cluster.

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</ref> This is one way to implement [[Massively parallel|massive parallelism]] in computing and can likewise be applied to [[In-memory processing|in-memory computing]].

A soft microprocessor and its surrounding peripherals implemented in a FPGA is less vulnerable to obsolescence than a discrete processor.<ref>{{Cite web

| author=Joe DeLaere.

[ | url=https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01255-top-7-reasons-to-replace-your-microcontroller-with-a-max-10-fpga.pdf
| title="Top 7 Reasons to Replace Your Microcontroller with a MAX 10 FPGA"].}}

</ref><ref>{{Cite web

|author1=John Swan; |author2=Tomek Krzyzak.

[ | url=http://www.embedded.com/print/4015159
| title="Using FPGAs to avoid microprocessor obsolescence"].

| date=2008

| archive-url=https://web.archive.org/web/20161013004106/http://www.embedded.com/print/4015159

</ref><ref>

| archive-date=2016-10-13

}}</ref><ref>

{{Cite web|url=https://www.electronicsweekly.com/news/products/fpga-news/fpga-processor-ip-needs-to-be-supported-2010-02/|title=FPGA processor IP needs to be supported|last=Staff|date=2010-02-03|website=Electronics Weekly|language=en-GB|access-date=2019-04-03}}

</ref>

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| [http://opencores.org/project,pavr Project page at Opencores]

| VHDL

|-

| softavrcore

| Andras Pal

| {{yes}}

| Standard AVR buses (core-coupled I/O, synchronous SRAM, synchronous program ROM)

| [[Atmel AVR]]-compatible 8-bit RISC (up to AVR5), peripherals and SoC features included

| [http://opencores.org/project/softavrcore Project page at Opencores]

| Verilog

|-

| colspan="7" align="center" | ''based on the [[MicroBlaze]] instruction set architecture''

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| OPB, FSL

| Binary compatible with the MicroBlaze

| [https://web.archive.org/web/20090724052731/http://www.ccm.ece.vt.edu/~scraven/openfire.html]<ref>{{Cite web|url=http://opencores.org/project,openfire_core,overview|title=Overview :: OpenFire Processor Core :: OpenCores}}</ref>

| Verilog

|-

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| [[University of Cambridge]]

| {{yes|BSD}}

|

| [[MIPS architecture|MIPS]]

| [http://www.cl.cam.ac.uk/research/security/ctsrd/beri/ Project page]

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| Pablo Bleyer

| {{yes}}

|

| Compatible with the PicoBlaze processors

| [http://bleyer.org/pacoblaze PacoBlaze]

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| {{yes|BSD}}

| Wishbone b4, AXI4

| rv32[i/e] [m] [a] [c] [b] [u] [Zfinx] [Zicsr] [Zifencei], RISC-V-compliant, CPU & SoC available, highly customizable, GCC toolchain

| [https://github.com/stnolting/neorv32 GitHub] [https://opencores.org/projects/neorv32 OpenCores]

| VHDL

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| {{Yes}}

|

| [[Manycore processor|Manycore]] [[SPARC|SPARC V9]]

| [http://parallel.princeton.edu/openpiton/specs.html OpenPiton]

| Verilog

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| HT-Lab

| {{yes}}

|

| 8088-compatible CPU in VHDL

| [http://www.ht-lab.com/cpu86.htm cpu86]

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| SystemVerilog

|-

| [[Zet (hardware)|Zet]]

| Zeus Gómez Marmolejo

| {{yes}}

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| Chisel

|-

| [[Libre-SoCSOC]]

| [https://libre-soc.org Libre-SoC.org]

| {{yes|BSD/LGPLv2+}}

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| python/nMigen

|-

| [[IBM_A2IBM A2#A2I|A2I]]

| IBM/OpenPOWER

| {{yes|CC-BY 4.0}}

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| VHDL

|-

| [[IBM_A2IBM A2#A2O|A2O]]

| IBM/OpenPOWER

| {{yes|CC-BY 4.0}}

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| [https://github.com/openpower-cores/a2o A2O @ Github]

| Verilog

|-

| colspan="7" align="center" | ''Other architectures''

|-

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| [[Synopsys#ARC International|ARC International]], [[Synopsys]]

| {{no}}

|

| 16/32/64-bit ISA RISC

| [https://www.synopsys.com/designware-ip/processor-solutions.html DesignWare ARC]

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| Entner Electronics

| {{no}}

|

| 9-bit RISC, very small size, C-programmable

| [http://www.entner-electronics.com/tl/index.php/eric5.html ERIC5] {{Webarchive|url=https://web.archive.org/web/20160305131214/http://www.entner-electronics.com/tl/index.php/eric5.html |date=2016-03-05 }}

| VHDL

|-

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| {{yes}}

| [[Wishbone (computer bus)|Wishbone]], B4/pipelined

| 32-bit RISC/Vector CPU withimplementing athe customMRISC32 ISA

| [https://mrisc32.bitsnbites.eu/ MRISC32]

| VHDL

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| Miguel Angel Ajo Pelayo

| {{yes|MIT}}

|

| PIC12F compatible, program synthesised in gates

| [http://projects.nbee.es/display/IPCORES/SYNPIC12+8bit+RISC+CPU+core nbee.es]

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| Verilog

|-

| [[ZPU_ZPU (microprocessor)|ZPU]]

| Zylin AS

| {{yes}}

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== See also ==

* [[System on a chip|System-on-a-chip]] (SoC)

** [[Network on a chip|Network-on-a-chip]] (NoC)

* [[Reconfigurable computing]]

** [[Field-programmable gate array]] (FPGA)

* [[VHDL]]

* [[Verilog]]

** [[SystemVerilog]]

* [[Hardware acceleration]]

==References==