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[[Image:Cray-1-deutsches-museum.jpg|thumb|A [[Cray-1]] supercomputer preserved at the [[Deutsches Museum]]]]
The
While the supercomputers of the 1980s used only a few processors, in the 1990s, machines with thousands of processors began to appear both in the United States and in Japan, setting new computational performance records.
By the end of the 20th century, massively parallel supercomputers with thousands of "off-the-shelf" processors similar to those found in personal computers were constructed and broke through the [[
Progress in the first decade of the 21st century was dramatic and supercomputers with over 60,000 processors appeared, reaching
==Beginnings: 1950s and 1960s==
{{see also|Vector processor#History|Vector Processor history}}
The term "Super Computing" was first used in the ''[[New York World]]'' in 1929<ref>{{cite book |last1=Eames |first1=Charles |last2=Eames |first2=Ray |title=A Computer Perspective |year=1973 |publisher=Harvard University Press |___location= Cambridge, Mass |pages = 95 }}. Page 95 identifies the article as {{cite news |title= Super Computing Machines Shown |publisher=New York World |date= March 1, 1920 }}. However, the article shown on page 95 references the Statistical Bureau in Hamilton Hall, and an article at the Columbia Computing History web site states that such did not exist until 1929. See [http://www.columbia.edu/acis/history/packard.html The Columbia Difference Tabulator - 1931]</ref> to refer to large custom-built [[Tabulating machine|tabulator]]s that [[IBM]] had made for [[Columbia University]].<ref>{{cite web | url=http://www.columbia.edu/cu/computinghistory/statlab-clipping.jpg|title= ''Super Computing Machines Shown'' (in ''New York World'') | year = 1920| access-date = 26 February 2024}}</ref>
There were several lines of second generation computers that were substantially faster than most contemporary mainframes. These included
In 1957, a group of engineers left [[Sperry Corporation]] to form [[Control Data Corporation]] (CDC) in [[Minneapolis]], Minnesota. [[Seymour Cray]] left Sperry a year later to join his colleagues at CDC.<ref name=chen >{{cite book | title = Hardware software co-design of a multimedia SOC platform | first1 = Sao-Jie | last1 = Chen | first2 = Guang-Huei | last2 = Lin | first3 = Pao-Ann | last3 = Hsiung | first4 = Yu-Hen | last4 = Hu | year = 2009 | isbn = 9781402096235 | pages = 70–72 | url = https://books.google.com/books?id=OXyo3om9ZOkC&pg=PA70 | publisher = [[Springer Science+Business Media]] | access-date = 20 February 2018}}</ref> In 1960, Cray completed the [[CDC 1604]], one of the first generation of commercially successful [[Transistor computer|transistorized]] computers and at the time of its release, the fastest computer in the world.<ref name=Hannan >{{cite book | title = Wisconsin Biographical Dictionary | first = Caryn | last = Hannan | year = 2008 | isbn = 978-1-878592-63-7 | pages = 83–84 | url = https://books.google.com/books?id=V08bjkJeXkAC&pg=PA83 | access-date = 20 February 2018}}</ref> However, the sole fully transistorized [[Harwell CADET]] was operational in 1951, and IBM delivered its commercially successful transistorized [[IBM 7090]] in 1959.▼
* [[Atlas (computer)|Atlas]]
* [[UNIVAC LARC]]
* [[IBM 7030]]
* [[IBM System/360 Model 91|IBM 360/91]]
* IBM 360/95
* [[CDC 6600]]
The second generation saw the introduction of features intended to support [[multiprogramming]] and [[multiprocessor]] configurations, including master/slave (supervisor/problem) mode, storage protection keys, limit registers, protection associated with address translation, and [[atomic instruction]]s.
▲In 1957, a group of engineers left [[Sperry Corporation]] to form [[Control Data Corporation]] (CDC) in [[Minneapolis]], Minnesota. [[Seymour Cray]] left Sperry a year later to join his colleagues at CDC.<ref name=chen >{{cite book | title = Hardware software co-design of a multimedia SOC platform | first1 = Sao-Jie | last1 = Chen | first2 = Guang-Huei | last2 = Lin | first3 = Pao-Ann | last3 = Hsiung | first4 = Yu-Hen | last4 = Hu | year = 2009 | isbn = 9781402096235 | pages = 70–72 | url = https://books.google.com/books?id=OXyo3om9ZOkC&pg=PA70 | publisher = [[Springer Science+Business Media]] | access-date = 20 February 2018}}</ref> In 1960, Cray completed the [[CDC 1604]], one of the first generation of commercially successful [[Transistor computer|transistorized]] computers and at the time of its release, the fastest computer in the world.<ref name=Hannan >{{cite book | title = Wisconsin Biographical Dictionary | first = Caryn | last = Hannan | year = 2008 | isbn = 978-1-878592-63-7 | pages = 83–84 | publisher = State History Publications | url = https://books.google.com/books?id=V08bjkJeXkAC&pg=PA83 | access-date = 20 February 2018}}</ref> However, the sole fully transistorized [[Harwell CADET]] was operational in 1951, and IBM delivered its commercially successful transistorized [[IBM 7090]] in 1959.
[[File:CDC 6600 introduced in 1964.jpg|thumb|left|The [[CDC 6600]] with the system console]]
Around 1960, Cray decided to design a computer that would be the fastest in the world by a large margin. After four years of experimentation along with Jim Thornton, and Dean Roush and about 30 other engineers, Cray completed the [[CDC 6600]] in 1964. Cray switched from germanium to silicon transistors, built by [[Fairchild Semiconductor]], that used the planar process. These did not have the drawbacks of the mesa silicon transistors. He ran them very fast, and the [[speed of light]] restriction forced a very compact design with severe overheating problems, which were solved by introducing refrigeration, designed by Dean Roush.<ref name="The Supermen 1997">{{cite book | title = The Supermen | first = Charles J. | last = Murray | publisher = Wiley & Sons | year = 1997 | isbn = 9780471048855 | url = https://books.google.com/books?id=VsA86kiUkC0C}}</ref> The 6600 outperformed the industry's prior recordholder, the [[IBM 7030 Stretch]],{{clarify|reason=How did the Stretch compare to the Atlas, numbers anybody? (see talk page)|date=January 2022}} by a factor of three.<ref name=AcadBook>"Designed by Seymour Cray, the CDC 6600 was almost three times faster than the next fastest machine of its day, the IBM 7030 Stretch." {{cite book
|title=Making a World of Difference: Engineering Ideas into Reality
|url=https://books.google.com/books?isbn=0309312655 |isbn=978-0309312653
|publisher=National Academy of Engineering |date=2014}}</ref><ref>"In 1964 Cray's CDC 6600 replaced Stretch as the fastest computer on Earth." {{cite book
|title=Expert Systems, Knowledge Engineering for Human Replication
|url=https://books.google.com/books?isbn=1291595090 |isbn=978-1291595093 |last=Sofroniou |first=Andreas |date=2013| publisher=Lulu.com }}</ref> With performance of up to three [[FLOPS|megaFLOPS]],<ref>{{cite web
| url=http://www.extremetech.com/extreme/125271-the-history-of-supercomputers
| first1= Sebastian | last1=Anthony
Line 33 ⟶ 43:
| website=Encyclopædia Britannica}}</ref> it was dubbed a ''supercomputer'' and defined the supercomputing market when two hundred computers were sold at $9 million each.<ref name=Hannan /><ref>{{cite book | title = A history of modern computing | publisher = MIT Press | first = Paul E. | last = Ceruzzi | year = 2003 | isbn = 978-0-262-53203-7 | page = [https://archive.org/details/historyofmodernc00ceru_0/page/161 161] | url = https://archive.org/details/historyofmodernc00ceru_0 | url-access = registration | access-date = 20 February 2018}}</ref>
The 6600 gained speed by "farming out" work to peripheral computing elements, freeing the CPU (Central Processing Unit) to process actual data. The Minnesota [[FORTRAN]] compiler for the machine was developed by Liddiard and Mundstock at the [[University of Minnesota]] and with it the 6600 could sustain 500 kiloflops on standard mathematical operations.<ref>{{cite journal | doi = 10.1145/361598.361914 | last =Frisch | first = Michael J. | date = December 1972 | title = Remarks on algorithm 352 [S22], algorithm 385 [S13], algorithm 392 [D3] | journal = Communications of the ACM | volume = 15 | issue = 12 | page = 1074| s2cid =6571977 | doi-access = free }}</ref> In 1968, Cray completed the [[CDC 7600]], again the fastest computer in the world.<ref name=Hannan /> At 36 [[Hertz|MHz]], the 7600 had 3.6 times the [[clock rate|clock speed]] of the 6600, but ran significantly faster due to other technical innovations. They sold only about 50 of the 7600s, not quite a failure. Cray left CDC in 1972 to form his own company.<ref name=Hannan /> Two years after his departure CDC delivered the [[CDC STAR-100|STAR-100]], which at 100 megaflops was three times the speed of the 7600. Along with the [[TI Advanced Scientific Computer|Texas Instruments ASC]], the STAR-100 was one of the first machines to use [[vector processing]]
[[File:University of Manchester Atlas, January 1963.JPG|thumb|The University of Manchester [[Atlas (computer)|Atlas]] in January 1963.]]
In 1956, a team at [[Manchester University]] in the United Kingdom began development of [[Manchester_computers#Muse_and_Atlas|MUSE]]
At the end of 1958, [[Ferranti#Computers|Ferranti]] agreed to collaborate with Manchester University on the project, and the computer was shortly afterwards renamed [[Atlas (computer)|Atlas]], with the joint venture under the control of [[Tom Kilburn]]. The first Atlas was officially commissioned on 7 December {{nowrap|1962
==The Cray era: mid-1970s and 1980s==
[[File:Cray2.jpeg|thumb|A
Four years after leaving CDC, Cray delivered the 80 MHz [[Cray-1]] in 1976, and it became the most successful supercomputer in history.<ref name=Hill41>{{cite book | title = Readings in computer architecture | first1 = Mark Donald | last1 = Hill |author-link2=Norman Jouppi | first2 = Norman Paul | last2 = Jouppi | first3 = Gurindar | last3 = Sohi | year = 1999 | isbn = 978-1-55860-539-8 | pages = 41–48| publisher = Gulf Professional }}</ref><ref name=Edwin65 /> The Cray-1, which used integrated circuits with two gates per chip, was a [[vector processor]]. It introduced a number of innovations, such as [[chaining (vector processing)|chaining]], in which scalar and vector registers generate interim results that can be used immediately, without additional memory references
The [[Cray-2]], released in 1985, was a four-processor [[Computer cooling|liquid cooled]] computer totally immersed in a tank of [[Fluorinert]], which bubbled as it operated.<ref name="The Supermen 1997" /> It reached 1.9 gigaflops and was the world's fastest supercomputer, and the first to break the gigaflop barrier.<ref>Due to Soviet propaganda, it can be read sometimes that the Soviet supercomputer M13 was the first to reach the gigaflops barrier. Actually, the M13 construction began in 1984, but it was not operational before 1986. [https://www.computer-museum.ru/english/galglory_en/Rogachev.php Rogachev Yury Vasilievich, Russian Virtual Computer Museum]</ref> The Cray-2 was a totally new design. It did not use chaining and had a high memory latency, but used much pipelining and was ideal for problems that required large amounts of memory.<ref name=Tokhi /> The software costs in developing a supercomputer should not be underestimated, as evidenced by the fact that in the 1980s the cost for software development at Cray came to equal what was spent on hardware.<ref name=MacKenzie >{{cite book | title = Knowing machines: essays on technical change | first = Donald | last = MacKenzie | year = 1998 | isbn = 0-262-63188-1 | pages = 149–151| publisher = MIT Press| url=https://archive.org/details/knowingmachinese0000mack/} }}</ref> That trend was partly responsible for a move away from the in-house, [[Cray Operating System]] to [[UNICOS]] based on [[Unix]].<ref name=MacKenzie />
The [[Cray Y-MP]], also designed by Steve Chen, was released in 1988 as an improvement of the X-MP and could have eight [[vector processor]]s at 167 MHz with a peak performance of 333 megaflops per processor.<ref name=Tokhi /> In the late 1980s, Cray's experiment on the use of [[gallium arsenide]] semiconductors in the [[Cray-3]] did not succeed. Seymour Cray began to work on a [[Multiple instruction, multiple data|massively parallel]] computer in the early 1990s, but died in a car accident in 1996 before it could be completed. Cray Research did, however, produce such computers.<ref name=Edwin65 >{{cite book | title = Milestones in computer science and information technology | url = https://archive.org/details/milestonesincomp0000reil | url-access = registration | first = Edwin D. | last = Reilly | year = 2003 | isbn = 1-57356-521-0 | page = [https://archive.org/details/milestonesincomp0000reil/page/65 65]| publisher = Bloomsbury Academic }}</ref><ref name="The Supermen 1997"/>
==Massive processing: the 1990s==
The [[Cray-2]] which set the frontiers of supercomputing in the mid to late 1980s had only 8 processors. In the 1990s, supercomputers with thousands of processors began to appear. Another development at the end of the 1980s was the arrival of Japanese supercomputers, some of which were modeled after the Cray-1.
During the first half of the [[Strategic Computing Initiative]], some massively parallel architectures were proven to work, such as the [[WARP (systolic array)|WARP systolic array]], message-passing [[Multiple instruction, multiple data|MIMD]] like the [[Caltech Cosmic Cube|Cosmic Cube]] hypercube, [[Single instruction, multiple data|SIMD]] like the [[Connection Machine]], etc. In 1987, a TeraOPS Computing Technology Program was proposed, with a goal of achieving 1 teraOPS (a trillion operations per second) by 1992, which was considered achievable by scaling up any of the previously proven architectures.<ref>{{Cite book |last1=Roland |first1=Alex |title=Strategic computing: DARPA and the quest for machine intelligence, 1983 - 1993 |last2=Shiman |first2=Philip |date=2002 |publisher=MIT Press |isbn=978-0-262-18226-3 |series=History of computing |___location=Cambridge, Mass. |pages=296}}</ref>
[[File:Paragon XP-E - mesh.jpg|thumb|left|Rear of the [[Intel Paragon|Paragon]] cabinet showing the bus bars and mesh routers]]
The [[SX-3 supercomputer|SX-3/44R]] was announced by [[NEC Corporation]] in 1989 and a year later earned the fastest-in-the-world title with a four-processor model.<ref>{{cite book | title = Computing methods in applied sciences and engineering | first1 = R. | last1 = Glowinski | first2 = A. | last2 = Lichnewsky | date = January 1990 | isbn = 0-89871-264-5 | pages = 353–360}}</ref> However, Fujitsu's [[Numerical Wind Tunnel]] supercomputer used 166 vector processors to gain the top spot in 1994. It had a peak speed of 1.7 gigaflops per processor.<ref>{{cite web | url = http://www.netlib.org/benchmark/top500/reports/report94/main.html | title = TOP500 Annual Report 1994 | date = 1 October 1996}}</ref><ref>{{Cite conference |first1=N. |last1= Hirose |first2= M. |last2= Fukuda |year=1997 |title=Numerical Wind Tunnel (NWT) and CFD Research at National Aerospace Laboratory |conference=Proceedings of HPC-Asia '97 |publisher=IEEE Computer Society |doi=10.1109/HPC.1997.592130}}</ref> The [[Hitachi SR2201]] obtained a peak performance of 600 gigaflops in 1996 by using 2,048 processors connected via a fast three-dimensional [[crossbar switch|crossbar]] network.<ref>{{cite conference | first1 = H. | last1 = Fujii | first2 = Y. | last2 = Yasuda | first3 = H. | last3 = Akashi | first4 = Y. | last4 = Inagami | first5 = M. | last5 = Koga | first6 = O. | last6 = Ishihara | first7 = M. | last7 = Kashiyama | first8 = H. | last8 = Wada | first9 = T. | last9 = Sumimoto | title = Architecture and performance of the Hitachi SR2201 massively parallel processor system |work = Proceedings of 11th International Parallel Processing Symposium | date = April 1997 | pages = 233–241 | doi = 10.1109/IPPS.1997.580901| isbn = 0-8186-7793-7 }}</ref><ref>{{cite journal | first = Y. | last = Iwasaki | title = The CP-PACS project | journal = Nuclear Physics B - Proceedings Supplements | volume = 60 | issue = 1–2 | date = January 1998 | pages = 246–254 | doi = 10.1016/S0920-5632(97)00487-8| arxiv = hep-lat/9709055 | bibcode = 1998NuPhS..60..246I }}</ref><ref>A.J. van der Steen, Overview of recent supercomputers, Publication of the NCF, Stichting Nationale Computer Faciliteiten, the Netherlands, January 1997.</ref>
In the same timeframe the [[Intel Paragon]] could have 1,000 to 4,000 [[Intel i860]] processors in various configurations, and was ranked the fastest in the world in 1993. The Paragon was a [[Multiple instruction, multiple data|MIMD]] machine which connected processors via a high speed two-dimensional mesh, allowing processes to execute on separate nodes; communicating via the [[Message Passing Interface]].<ref>{{cite book | title = Scalable input/output: achieving system balance | first = Daniel A. | last = Reed | year = 2003 | isbn = 978-0-262-68142-1 | page = 182| publisher = MIT Press }}</ref> By 1995, Cray was also shipping massively parallel systems, e.g. the [[Cray T3E]] with over 2,000 processors, using a three-dimensional [[torus interconnect]].<ref>{{cite press release | title = Cray Sells First T3E-1350 Supercomputer to PhillipsPetroleum | agency = Business Wire | publisher = Gale Group | date = 7 August 2000 | url = https://www.thefreelibrary.com/Cray+Sells+First+T3E-1350+Supercomputer+to+Phillips+Petroleum.-a063900928 | ___location = Seattle }}</ref><ref name=Torus>{{cite journal|first=N. R.|last=Agida|collaboration = et al.|title=Blue Gene/L Torus Interconnection Network|journal=[[IBM Journal of Research and Development]]|volume=45|number=2–3|date=March–May 2005|page=265|url=http://www.cc.gatech.edu/classes/AY2008/cs8803hpc_spring/papers/bgLtorusnetwork.pdf |access-date=9 February 2012 |url-status=dead |archive-url=https://web.archive.org/web/20110815102821/http://www.cc.gatech.edu/classes/AY2008/cs8803hpc_spring/papers/bgLtorusnetwork.pdf |archive-date=15 August 2011 }}</ref>
The Paragon architecture soon led to the Intel [[ASCI Red]] supercomputer in the United States, which held the top supercomputing spot to the end of the 20th century as part of the [[Advanced Simulation and Computing Initiative]]. This was also a mesh-based MIMD massively-parallel system with over 9,000 compute nodes and well over 12 terabytes of disk storage, but used off-the-shelf [[Pentium Pro]] processors that could be found in everyday personal computers. ASCI Red was the first system ever to break through the 1 teraflop barrier on the MP-[[Linpack]] benchmark in 1996; eventually reaching 2 teraflops.<ref>{{cite journal | journal = Algorithms for Parallel Processing | title = Enabling Department-Scale Supercomputing | volume = 105 | first = David S. | last = Greenberg | editor-first = Michael T. | editor-last = Heath | year = 1998 | isbn = 0-387-98680-4 | page = 323 | url = https://books.google.com/books?id=zo61nbirb_gC&pg=PA323 | access-date = 20 February 2018}}</ref>
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[[Image:IBM Blue Gene P supercomputer.jpg|240px|thumb|A [[Blue Gene]]/P supercomputer at [[Argonne National Laboratory]]]]
Significant progress was made in the first decade of the 21st century. The efficiency of supercomputers continued to increase, but not dramatically so. The [[Cray C90]] used 500 kilowatts of power in 1991, while by 2003 the [[ASCI Q]] used 3,000 kW while being 2,000 times faster, increasing the performance per watt 300 fold.<ref name=WuFeng>{{cite journal | first = Wu-chun | last = Feng | title = Making a Case for Efficient Supercomputing | journal = ACM Queue
In 2004, the [[Earth Simulator]] supercomputer built by [[NEC]] at the Japan Agency for Marine-Earth Science and Technology (JAMSTEC) reached 35.9 teraflops, using 640 nodes, each with eight proprietary [[vector processor]]s.<ref>{{cite journal | first = Tetsuya | last = Sato | title = The Earth Simulator: Roles and Impacts | journal = Nuclear Physics B: Proceedings Supplements | page = 102 | volume = 129 | doi = 10.1016/S0920-5632(03)02511-8 | year = 2004| bibcode = 2004NuPhS.129..102S }}</ref>
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The [[IBM]] [[Blue Gene]] supercomputer architecture found widespread use in the early part of the 21st century, and 27 of the computers on the [[TOP500]] list used that architecture. The Blue Gene approach is somewhat different in that it trades processor speed for low power consumption so that a larger number of processors can be used at air cooled temperatures. It can use over 60,000 processors, with 2048 processors "per rack", and connects them via a three-dimensional torus interconnect.<ref>{{cite conference | title = Early Experience with Scientific Applications on the Blue Gene/L Supercomputer | first = George | last = Almasi | collaboration = et al. | work = Euro-Par 2005 parallel processing: 11th International Euro-Par Conference | editor1-first = José Cardoso | editor1-last = Cunha | editor2-first = Pedro D. | editor2-last = Medeiros | year = 2005 | pages = 560–567 | isbn = 9783540319252 | url = https://books.google.com/books?id=RCEHCAAAQBAJ&pg=PA560}}</ref><ref>{{cite news | title = IBM uncloaks 20 petaflops BlueGene/Q super | url = https://www.theregister.co.uk/2010/11/22/ibm_blue_gene_q_super/ | work = The Register | date = 22 November 2010 | first = Timothy Prickett | last = Morgan}}</ref>
Progress in [[China]] has been rapid, in that China placed 51st on the TOP500 list in June 2003
In July 2011, the 8.1 petaflop Japanese [[K computer]] became the fastest in the world, using over 60,000 [[SPARC64 V#SPARC64 VIIIfx|SPARC64 VIIIfx]] processors housed in over 600 cabinets. The fact that the K computer is over 60 times faster than the Earth Simulator, and that the Earth Simulator ranks as the 68th system in the world seven years after holding the top spot, demonstrates both the rapid increase in top performance and the widespread growth of supercomputing technology worldwide.<ref name=tele20611>{{cite news|url=https://www.telegraph.co.uk/technology/news/8586655/Japanese-supercomputer-K-is-worlds-fastest.html|title=Japanese supercomputer 'K' is world's fastest|access-date=20 June 2011|work=The Telegraph|date=20 June 2011}}</ref><ref name=nyt20611>{{cite news|url=https://www.nytimes.com/2011/06/20/technology/20computer.html|title=Japanese 'K' Computer Is Ranked Most Powerful|access-date=20 June 2011|work=The New York Times|date=20 June 2011}}</ref><ref name=fujnr>{{cite web|url=http://www.fujitsu.com/global/news/pr/archives/month/2011/20110620-02.html|title=Supercomputer 'K computer' Takes First Place in World|access-date=20 June 2011|publisher=Fujitsu}}</ref> By 2014, the Earth Simulator had dropped off the list and by 2018 the K computer had dropped out of the top 10. By 2018, [[Summit (supercomputer)|Summit]] had become the world's most powerful supercomputer, at 200 petaFLOPS. In 2020, the Japanese once again took the top spot with the [[Fugaku (supercomputer)|Fugaku supercomputer]], capable of 442 PFLOPS. Finally, starting in 2022 and until the present ({{as of|December 2023|lc=y}}), the [[TOP500|world's fastest supercomputer]] had become the Hewlett Packard Enterprise [[Frontier (supercomputer)|Frontier]], also known as the OLCF-5 and hosted at the [[Oak Ridge Leadership Computing Facility]] (OLCF) in [[Tennessee]], United States. The Frontier is based on the [[Cray#Subsidiary of Hewlett Packard Enterprise: 2019–present|Cray EX]], is the world's first [[Exascale computing|exascale]] [[supercomputer]], and uses only [[AMD]] [[CPU]]s and [[GPU]]s; it achieved an [[LINPACK benchmarks#HPLinpack|Rmax]] of 1.102 [[FLOPS|exaFLOPS]], which is 1.102 quintillion operations per second.<ref>{{cite web |last1=Wells |first1=Jack |date=March 19, 2018 |title=Powering the Road to National HPC Leadership |url=https://www.youtube.com/watch?v=9tmWN9PR-ZU&t=2h24m41s |publisher=OpenPOWER Summit 2018 |access-date=March 25, 2018 |archive-date=August 4, 2020 |archive-url=https://web.archive.org/web/20200804004021/https://www.youtube.com/watch?v=9tmWN9PR-ZU&t=2h24m41s |url-status=live }}</ref><ref>{{cite web |last1=Bethea |first1=Katie |date=February 13, 2018 |title=Frontier: OLCF'S Exascale Future – Oak Ridge Leadership Computing Facility |url=https://www.olcf.ornl.gov/2018/02/13/frontier-olcfs-exascale-future/ |url-status=live |archive-url=https://web.archive.org/web/20180310203823/https://www.olcf.ornl.gov/2018/02/13/frontier-olcfs-exascale-future/ |archive-date=March 10, 2018 |website=Oak Ridge National Laboratory - Leadership Computing Facility}}</ref><ref>{{Cite web |date=October 9, 2020 |title=DOE Under Secretary for Science Dabbar's Exascale Update |url=https://insidehpc.com/2020/10/doe-under-secretary-for-science-dabbars-exascale-update-frontier-to-be-first-aurora-to-be-monitored/ |url-status=live |archive-url=https://web.archive.org/web/20201028093045/https://insidehpc.com/2020/10/doe-under-secretary-for-science-dabbars-exascale-update-frontier-to-be-first-aurora-to-be-monitored/ |archive-date=October 28, 2020 |website=insideHPC}}</ref><ref>{{cite news |author=Don Clark |date=May 30, 2022 |title=U.S. Retakes Top Spot in Supercomputer Race |work=The New York Times |url=https://www.nytimes.com/2022/05/30/business/us-supercomputer-frontier.html |access-date=June 1, 2022 |archive-date=June 1, 2022 |archive-url=https://web.archive.org/web/20220601230913/https://www.nytimes.com/2022/05/30/business/us-supercomputer-frontier.html |url-status=live }}</ref><ref>{{cite news |last1=Larabel |first1=Michael |title=AMD-Powered Frontier Supercomputer Tops Top500 At 1.1 Exaflops, Tops Green500 Too |url=https://www.phoronix.com/scan.php?page=news_item&px=Top500-Green500-Frontier |access-date=June 1, 2022 |website=[[Phoronix]] |date=May 30, 2022 |language=en |archive-date=June 6, 2022 |archive-url=https://web.archive.org/web/20220606064113/https://www.phoronix.com/scan.php?page=news_item&px=Top500-Green500-Frontier |url-status=live }}</ref>
==Historical TOP500 table==
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|[[Riken]], [[Kobe]], [[Japan]]
|-
|2021
|[[Frontier_(supercomputer)|Frontier]]
|align=right|>1.1 EFLOPS
|
|[[Oak Ridge Leadership Computing Facility]],
|-
<!-- Please do not add new computers unless they appear as #1 on the TOP500 list. See discussion page.-->
|}
==Export controls==
The [[CoCom]] and its later replacement, the [[Wassenaar Arrangement]], legally regulated, i.e. required licensing and approval and record-keeping; or banned entirely, the export of [[high-performance computer]]s (HPCs) to certain countries. Such controls have become harder to justify, leading to loosening of these regulations. Some have argued these regulations were never justified.<ref>{{cite book | url = http://www.princeton.edu/~ota/disk1/1994/9408/940810.PDF | section = Complexities of Setting Export Control Thresholds: Computers | title = Export controls and nonproliferation policy | publisher = DIANE Publishing | isbn = 9781428920521 | date = May 1994}}</ref><ref>{{cite journal | first1 = Peter | last1 = Wolcott | first2 = Seymour | last2 = Goodman | first3 = Patrick | last3 = Homer | url = http://www.isqa.unomaha.edu/wolcott/Publications/vpcacm.htm | title = High Performance Computing Export Controls: Navigating Choppy Waters | journal = Communications of the ACM | date = November 1998 | volume = 41 | issue = 11 | pages = 27–30 | doi = 10.1145/287831.287836 | ___location = New York, USA| s2cid = 18519822 | doi-access = free }}</ref><ref>{{cite report | first1 = Glenn J. | last1 = McLoughlin | first2 = Ian F. | last2 = Fergusson | url = http://www.fas.org/sgp/crs/RL31175.pdf | title = High Performance Computers and Export Control Policy | date = 10 February 2003}}</ref><ref>{{cite web | first = Seth | last = Brugger | url = http://www.armscontrol.org/act/2000_09/exportsept00 | title = U.S. Revises Computer Export Control Regulations | date = 1 September 2000 | website = [[Arms Control Association]]}}</ref><ref>{{cite web | url = https://www.federalregister.gov/articles/2011/06/24/2011-15842/export-controls-for-high-performance-computers-wassenaar-arrangement-agreement-implementation-for | title = Export Controls for High Performance Computers | date = 24 June 2011}}</ref><ref>{{cite news | first = Jeff | last = Blagdon | url = https://www.theverge.com/2013/5/30/4381592/us-removes-sanctions-on-computer-exports-to-iran | title = US removes sanctions on computer exports to Iran | date = 30 May 2013}}</ref>
==See also==
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* [[Supercomputing in Japan]]
* [[Supercomputing in Pakistan]]
==References==▼
{{Reflist|2}}▼
==External links==
*[https://www.computerhistory.org/visiblestorage/1960s-1980s/supercomputers/ Supercomputers (1960s-1980s)] at the [[Computer History Museum]]
*[https://www.cs.cmu.edu/afs/cs/academic/class/15740-f03/public/doc/discussions/uniprocessors/vector/vector-past-present-future-supercomputing98.pdf R. Espasa, M. Valero, and J. E. Smith, “Vector architectures: past, present and future,” in Proceedings of the 12th international conference on Supercomputing, 1998]
[[Category:Supercomputers]]
[[Category:History of computing hardware|Supercomputing]]
[[Category:History of Silicon Valley|Supercomputing]]
▲==References==
▲{{Reflist|2}}
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