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{{Short description|Use of computer hardware to assist software in the process of data encryption}}
{{Infobox industrial process
|type=[[Cryptography]]
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|caption = The [[IBM 4758]] Cryptographic Module
}}
'''Hardware-based encryption''' is the use of [[computer hardware]] to assist software, or sometimes replace software, in the process of data [[encryption]]. Typically, this is implemented as part of the [[CPU|processor]]'s [[Instruction set architecture|instruction set]]. For example, the [[Advanced Encryption Standard|AES]] encryption algorithm (a modern [[cipher]]) can be implemented using the [[AES instruction set]] on the ubiquitous [[x86 architecture]].<ref name="Intel AES Instructions" /> Such instructions also exist on the [[ARM architecture]].<ref name="cortex cryptography" /> However, more unusual systems exist where the cryptography module is separate from the central processor, instead being implemented as a [[coprocessor]], in particular a [[secure cryptoprocessor]] or [[cryptographic accelerator]], of which an example is the [[IBM 4758]], or its successor, the [[IBM 4764]].<ref name="IBM 4764" /> Hardware implementations can be faster and less prone to exploitation than traditional software implementations, and furthermore can be protected against tampering.<ref name="performance
== History ==
== Implementations ==
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==== x86 ====
{{Main|AES instruction set|Intel SHA extensions}}
The [[X86]] [[Computer architecture|architecture]], as a [[Complex instruction set computer|CISC (Complex Instruction Set Computer)]] Architecture, typically implements complex [[algorithms]] in hardware.<ref name="Oxford" /> Cryptographic algorithms are no exception. The x86 architecture implements significant components of the [[Advanced Encryption Standard|AES (Advanced Encryption Standard)]] algorithm,<ref name="Intel AES Instructions" /> which can be used by the [[NSA]] for [[Top Secret]] information.<ref name="NIST National Security" /> The architecture also includes support for the [[Secure Hash Algorithms|SHA]] Hashing Algorithms through the [[Intel SHA extensions]].<ref name="Intel AES Instructions" /> Whereas AES is a cipher, which is useful for encrypting documents, [[Hash function|
==== ARM ====
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=== As a coprocessor ===
* [[IBM 4758]]
* [[IBM 4764]] and [[IBM 4765]], identical except for the connection used.<ref name="NIST approval" /> The former uses [[PCI-X]], while the latter uses [[PCI-e]].<ref name="IBM 4764" /> Both are [[peripheral devices]] that plug into the [[motherboard]].
=== Proliferation ===
[[Advanced Micro Devices]] (AMD) processors are also x86 devices, and have supported the [[AES instruction set|AES instructions]] since the 2011 [[Bulldozer (microarchitecture)|Bulldozer]] processor iteration.
Due to the existence of encryption instructions on modern processors provided by both [[Intel]] and AMD, the instructions are present on most modern computers.<ref name="Haifa" /> They also exist on many tablets and smartphones due to their implementation in [[ARM architecture|ARM processors]].<ref name="Haifa" />
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== Disadvantages ==
If, however, the hardware implementation is compromised, major issues arise. Malicious software can retrieve the data from the (supposedly) secure hardware
==See also==
* [[Disk encryption hardware]]
* [[Hardware-based full disk encryption]]
* [[Hardware security module]]
==References==
{{Reflist|30em|refs=
<ref name="Intel AES Instructions">{{cite book|title=Intel® 64 and IA-32 Architectures Software
<ref name="cortex cryptography">{{cite book|title=ARM® Cortex®-A57 MPCore Processor Cryptography Extension|date=
<ref name="IBM 4764">{{cite web|url=https://www.ibm.com/support/knowledgecenter/ssw_ibm_i_61/rzajc/rzajcco4758.htm|title=4764 Cryptographic Coprocessor|publisher=IBM|access-date=
<ref name="performance">{{cite web|title=AES-NI Performance Analyzed|url=http://www.tomshardware.com/reviews/clarkdale-aes-ni-encryption,2538.html|publisher=Tom's Hardware|year=2010|author=P. Schmid and A. Roos |
<ref name="
<ref name="
<ref name="
<ref name="consumers">{{cite web | url=http://ecommercenews.eu/consumers-online-shopping-expectations/ | title=Consumers and their online shopping expectations – Ecommerce News | date=
<ref name="Oxford">{{cite web|url=https://www.cs.ox.ac.uk/teaching/materials17-18/ca/lecture03.pdf|title=x86-64 Instruction Set|publisher=[[University of Oxford]]|pages=1|date=
▲<ref name="consumers">{{cite web | url=http://ecommercenews.eu/consumers-online-shopping-expectations/ | title=Consumers and their online shopping expectations – Ecommerce News | date={{date|2015-2-20}}| accessdate={{date|2016-08-29}}}}</ref>
<ref name="NIST National Security">{{cite web |url=http://csrc.nist.gov/groups/ST/toolkit/documents/aes/CNSS15FS.pdf |title=National Policy on the Use of the Advanced Encryption Standard (AES) to Protect National Security Systems and National Security Information |author=Lynn Hathaway |date=
▲<ref name="Oxford">{{cite web|url=https://www.cs.ox.ac.uk/teaching/materials17-18/ca/lecture03.pdf|title=x86-64 Instruction Set|publisher=[[University of Oxford]]|pages=1|date={{date|2017-04-18}}|access-date={{date|2018-01-24}}}}</ref>
<ref name="IBM 4758 datasheet">{{cite web|url=ftp://www6.software.ibm.com/software/cryptocards/G221-9091-04.pdf|title=IBM 4758 Models 2 and 23 PCI Cryptographic Coprocessor|date=
▲<ref name="NIST National Security">{{cite web|url=http://csrc.nist.gov/groups/ST/toolkit/documents/aes/CNSS15FS.pdf |title=National Policy on the Use of the Advanced Encryption Standard (AES) to Protect National Security Systems and National Security Information |author=Lynn Hathaway |date={{date|June 2003}}|format=PDF |access-date={{date|2011-02-15}}}}</ref>
<ref name="openwrt">{{cite web|url=http://wiki.openwrt.org/doc/hardware/cryptographic.hardware.accelerators|title=Cryptographic Hardware Accelerators|publisher=OpenWRT.org|date=
▲<ref name="IBM 4758 datasheet">{{cite web|url=ftp://www6.software.ibm.com/software/cryptocards/G221-9091-04.pdf|title=IBM 4758 Models 2 and 23 PCI Cryptographic Coprocessor|date={{date|May 2004}}|access-date={{date|2018-01-24}}|publisher=[[IBM]]}}</ref>
<ref name="NIST approval">{{cite web|url=https://csrc.nist.gov/csrc/media/projects/cryptographic-module-validation-program/documents/security-policies/140sp1505.pdf|date=
▲<ref name="openwrt">{{cite web|url=http://wiki.openwrt.org/doc/hardware/cryptographic.hardware.accelerators|title=Cryptographic Hardware Accelerators|publisher=OpenWRT.org|date={{date|2016-05-17}}|access-date={{date|2018-01-25}}}}</ref>
<ref name="Arecibo Bulldozer">{{cite web|url=https://www.naic.edu/~phil/software/amd/New-Bulldozer-and-Piledriver-Instructions-1.pdf|date=
▲<ref name="NIST approval">{{cite web|url=https://csrc.nist.gov/csrc/media/projects/cryptographic-module-validation-program/documents/security-policies/140sp1505.pdf|date={{date|2012-12-10}}|access-date={{date|2018-01-20}}|title=IBM 4765 Cryptographic Coprocessor Security Module|publisher=[[National Institute of Standards and Technology]]}}</ref>
<ref name="Haifa">{{cite web|url=https://eprint.iacr.org/2016/122.pdf|title=Simpira v2: A Family of Efficient Permutations Using the AES Round Function|date=
▲<ref name="Arecibo Bulldozer">{{cite web|url=https://www.naic.edu/~phil/software/amd/New-Bulldozer-and-Piledriver-Instructions-1.pdf|date={{date|October 2012}}|access-date={{date|2018-01-25}}|title=New “Bulldozer” and “Piledriver” Instructions|publisher=[[Arecibo Observatory]]|author=Brent Hollingsworth ([[Advanced Micro Devices|AMD]])}}</ref>
<ref name="Intel SGX">{{cite web |url=https://software.intel.com/en-us/blogs/2013/09/26/protecting-application-secrets-with-intel-sgx |title=Intel SGX for Dummies (Intel SGX Design Objectives) |work=intel.com |date=2013-09-26 |url-status=live |archive-url=https://web.archive.org/web/20140429161139/https://software.intel.com/en-us/blogs/2013/09/26/protecting-application-secrets-with-intel-sgx |archive-date=2014-04-29 }}</ref>▼
▲<ref name="Haifa">{{cite web|url=https://eprint.iacr.org/2016/122.pdf|title=Simpira v2: A Family of Efficient Permutations Using the AES Round Function|date={{date|2016-11-09}}|access-date={{date|2018-01-25}}|author=Shay Gueron ([[University of Haifa]] & [[Intel]]) and Nicky Mouha ([[KU Leuven]] & [[NIST]])}}</ref>
<ref name="BearSSL">{{Cite web|url=https://www.bearssl.org/constanttime.html|title=BearSSL – Constant-Time Crypto|website=www.bearssl.org|access-date=2017-01-10|url-status=live|archive-url=https://web.archive.org/web/20170111003347/https://www.bearssl.org/constanttime.html|archive-date=2017-01-11}}</ref>▼
▲<ref name="Intel SGX">{{cite web|url=https://software.intel.com/en-us/blogs/2013/09/26/protecting-application-secrets-with-intel-sgx |title=Intel SGX for Dummies (Intel SGX Design Objectives) |work=intel.com |date=2013-09-26}}</ref>
<ref name="PCW-20180109">{{cite web |author-last=Hachman |author-first=Mark |title=Microsoft tests show Spectre patches drag down performance on older PCs |url=https://www.pcworld.com/article/3245742/components-processors/microsoft-tests-show-spectre-patches-drag-down-performance-on-older-pcs.html |date=January 9, 2018 |work=[[PC World]] |access-date=2018-01-09 |url-status=live |archive-url=https://web.archive.org/web/20180209120423/https://www.pcworld.com/article/3245742/components-processors/microsoft-tests-show-spectre-patches-drag-down-performance-on-older-pcs.html |archive-date=February 9, 2018 }}</ref>▼
▲<ref name="BearSSL">{{Cite web|url=https://www.bearssl.org/constanttime.html|title=BearSSL – Constant-Time Crypto|website=www.bearssl.org|access-date=2017-01-10}}</ref>
▲<ref name="PCW-20180109">{{cite web |author-last=Hachman |author-first=Mark |title=Microsoft tests show Spectre patches drag down performance on older PCs |url=https://www.pcworld.com/article/3245742/components-processors/microsoft-tests-show-spectre-patches-drag-down-performance-on-older-pcs.html |date=January 9, 2018 |work=[[PC World]] |access-date=2018-01-09}}</ref>
}}
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