Instruction set architecture: Difference between revisions

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{{Machine code}}

An '''instruction set architecture''' ('''ISA''') is an [[abstract model]] that defines the programmable [[interface (computing)|interface]] of the [[CPU]] of a computer; how [[software]] can control a computer.<ref>{{Cite web |title=GLOSSARY: Instruction Set Architecture (ISA) |url=https://www.arm.com/glossary/isa |archive-url=https://web.archive.org/web/20231111175250/https://www.arm.com/glossary/isa |archive-date=2023-11-11 |access-date=2024-02-03 |website=arm.com}}</ref> A device (i.e. CPU) that interprets instructions described by an ISA is an [[implementation]] of that ISA. Generally, the same ISA is used for a family of related CPU devices.

In general, an ISA defines the [[Machine code|instructions]], [[data type]]s, [[Register (computer)|registers]], the hardware support for managing [[Computer memory|main memory]],{{Clarify|date=April 2024|reason=See "What does "Hardware support for managing main memory" refer to?" on the talk page.]]}} fundamental features (such as the [[memory consistency]], [[addressing mode]]s, [[virtual memory]]), and the [[input/output]] model of the programmable interface.

An ISA specifies the behavior implied by [[machine code]] running on an implementation of that ISA in a fashion that does not depend on the characteristics of that implementation, providing [[binary compatibility]] between implementations. This enables multiple implementations of an ISA that differ in characteristics such as [[Computer performance|performance]], physical size, and monetary cost (among other things), but that are capable of running the same machine code, so that a lower-performance, lower-cost machine can be replaced with a higher-cost, higher-performance machine without having to replace software. It also enables the evolution of the [[microarchitecture]]s of the implementations of that ISA, so that a newer, higher-performance implementation of an ISA can run software that runs on previous generations of implementations.

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*''[[Conditional branch|Conditionally branch]]'' to another ___location if a certain condition holds.

*''[[Indirect branch|Indirectly branch]]'' to another ___location.

*''Skip'' one ofor more instructions, depending on conditions, known(a asconditional [[Predication_(computer_architecturebranch a fixed number of instructions forward)|predication]]

*''Trap'' Explicitly cause an [[interrupt]], either conditionally or unconditionally.

*''[[Subroutine|Call]]'' another block of code, while saving, e.g., the ___location of the next instruction, as a point to return to.

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*Load/store data to and from a coprocessor or exchanging with CPU registers.

*Perform coprocessor operations.

Early historic:Some examples of coprocessor instructions include those for the [[IBM 3090]] [[IBM_3090IBM 3090#Vector_facilityVector facility|Vector facility]] and the [[Intel 8087]].

===Complex instructions===

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Most [[stack machine]]s have "[[0-operand instruction set|0-operand]]" instruction sets in which arithmetic and logical operations lack any operand specifier fields; only instructions that push operands onto the evaluation stack or that pop operands from the stack into variables have operand specifiers. The instruction set carries out most ALU actions with postfix ([[reverse Polish notation]]) operations that work only on the expression [[Stack (abstract data type)|stack]], not on data registers or arbitrary main memory cells. This can be very convenient for compiling high-level languages, because most arithmetic expressions can be easily translated into postfix notation.<ref>{{cite web|url=http://www.cs.kent.edu/~durand/CS0/Notes/Chapter05/isa.html|title=Instruction Set Architecture (ISA)|work=Introduction to Computer Science CS 0|first=Paul|last=Durand}}</ref>

====Conditional instructions====

<!-- A conditional branch that falls though may still have other effects, e.g., decrementing a count register. -->

Conditional instructions often have a predicate field—a few bits that encode the specific condition to cause an operation to be performed rather than not performed. For example, a conditional branch instruction will transfer control if the condition is true, so that execution proceeds to a different part of the program, and not transfer control if the condition is false, so that execution continues sequentially. Some instruction sets also have conditional moves, so that the move will be executed, and the data stored in the target ___location, if the condition is true, and not executed, and the target ___location not modified, if the condition is false. Similarly, IBM [[z/Architecture]] has a conditional store instruction. A few instruction sets include a predicate field in every instruction. Having predicates for non-branchon instructions is called [[predication (computer architecture)|predication]], and can ''include'' conditional-branches, such as {{code|bf}} on the [[SuperH]].<ref>https://shared-ptr.com/sh_insns.html</ref>

====Number of operands====

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*more operands—some CISC machines permit a variety of addressing modes that allow more than 3 operands (registers or memory accesses), such as the [[VAX]] "POLY" polynomial evaluation instruction.

Due to the large number of bits needed to encode the three registers of a 3-operand instruction, RISC architectures that have 16-bit instructions are invariably 2-operand designs, such as the Atmel AVR, [[TI MSP430]], and some versions of [[ARM Thumb]]. RISC architectures that have 32-bit instructions are usually 3-operand designs, such as the [[ARM architecture family|ARM]], [[AVR32]], [[MIPS architecture|MIPS]], [[Power ISA]], and [[SPARC]] architectures. However even 3-operand RISC architectures will, at considerable cost, have [[Multiply%E2%80%93accumulate_operation#Fused_multiply%E2%80%93add|Fused multiply-and-add]] 4-operand instructions out of necessity, due to the increased accuracy provided. Modern examples include [[Power ISA]] and [[RISC-V]].

Each instruction specifies some number of operands (registers, memory locations, or immediate values) ''explicitly''. Some instructions give one or both operands implicitly, such as by being stored on top of the [[stack (data structure)|stack]] or in an implicit register. If some of the operands are given implicitly, fewer operands need be specified in the instruction. When a "destination operand" explicitly specifies the destination, an additional operand must be supplied. Consequently, the number of operands encoded in an instruction may differ from the mathematically necessary number of arguments for a logical or arithmetic operation (the [[arity]]). Operands are either encoded in the "opcode" representation of the instruction, or else are given as values or addresses following the opcode.

==={{Anchor|REGISTER-PRESSURE}}Register pressure===

''Register pressure'' measures the availability of free registers at any point in time during the program execution. Register pressure is high when a large number of the available registers are in use;. thusThus, the higher the register pressure, the more often the register contents must be [[register spilling|spilled]] into cache or memory which, given their slower speed, exacts a heavy price. Increasing the number of registers in an architecture decreases register pressure but increases the cost.<ref>{{cite book |last=Page |first=Daniel |title=A Practical Introduction to Computer Architecture |chapter=11. Compilers |year=2009 |publisher=Springer |isbn=978-1-84882-255-9 |page=464|bibcode=2009pica.book.....P }}</ref>

While embedded instruction sets such as [[ARM Thumb|Thumb]] suffer from extremely high register pressure because they have small register sets, general-purpose RISC ISAs like [[MIPS architecture|MIPS]] and [[DEC Alpha|Alpha]] enjoy low register pressure. CISC ISAs like x86-64 offer low register pressure despite having smaller register sets. This is due to the many addressing modes and optimizations (such as sub-register addressing, memory operands in ALU instructions, absolute addressing, PC-relative addressing, and register-to-register spills) that CISC ISAs offer.<ref>{{cite conference |last1=Venkat |first1=Ashish |last2=Tullsen |first2=Dean M. |title=Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor |year=2014 |conference=41st Annual International Symposium on Computer Architecture |url=http://dl.acm.org/citation.cfm?id=2665692}}</ref>