Instruction set architecture: Difference between revisions

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{{Machine code}}

An '''instruction set architecture''' ('''ISA''') is an [[abstract model]] that defines the programmable [[interface (computing)|interface]] of the [[CPU]] of a computer; how [[software]] can control a computer.<ref>{{Cite web |title=GLOSSARY: Instruction Set Architecture (ISA) |url=https://www.arm.com/glossary/isa |archive-url=https://web.archive.org/web/20231111175250/https://www.arm.com/glossary/isa |archive-date=2023-11-11 |access-date=2024-02-03 |website=arm.com}}</ref> A device (i.e. CPU) that interprets instructions described by an ISA is an [[implementation]] of that ISA. Generally, the same ISA is used for a family of related CPU devices.

In general, an ISA defines the [[Machine code|instructions]], [[data type]]s, [[Register (computer)|registers]], the hardware support for managing [[Computer memory|main memory]],{{Clarify|date=April 2024|reason=See "What does "Hardware support for managing main memory" refer to?" on the talk page.]]}} fundamental features (such as the [[memory consistency]], [[addressing mode]]s, [[virtual memory]]), and the [[input/output]] model of the programmable interface.

An ISA specifies the behavior implied by [[machine code]] running on an implementation of that ISA in a fashion that does not depend on the characteristics of that implementation, providing [[binary compatibility]] between implementations. This enables multiple implementations of an ISA that differ in characteristics such as [[Computer performance|performance]], physical size, and monetary cost (among other things), but that are capable of running the same machine code, so that a lower-performance, lower-cost machine can be replaced with a higher-cost, higher-performance machine without having to replace software. It also enables the evolution of the [[microarchitecture]]s of the implementations of that ISA, so that a newer, higher-performance implementation of an ISA can run software that runs on previous generations of implementations.

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*''[[Conditional branch|Conditionally branch]]'' to another ___location if a certain condition holds.

*''[[Indirect branch|Indirectly branch]]'' to another ___location.

*''Skip'' one ofor more instructions, depending on conditions, known(a asconditional [[Predication_(computer_architecturebranch a fixed number of instructions forward)|predication]]

*''Trap'' Explicitly cause an [[interrupt]], either conditionally or unconditionally.

*''[[Subroutine|Call]]'' another block of code, while saving, e.g., the ___location of the next instruction, as a point to return to.

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*Load/store data to and from a coprocessor or exchanging with CPU registers.

*Perform coprocessor operations.

Early historic:Some examples of coprocessor instructions include those for the [[IBM 3090]] [[IBM_3090IBM 3090#Vector_facilityVector facility|Vector facility]] and the [[Intel 8087]].

===Complex instructions===

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==={{Anchor|REGISTER-PRESSURE}}Register pressure===

''Register pressure'' measures the availability of free registers at any point in time during the program execution. Register pressure is high when a large number of the available registers are in use;. thusThus, the higher the register pressure, the more often the register contents must be [[register spilling|spilled]] into cache or memory, which, given thetheir slower speed of memory, exacts a heavy price. Increasing the number of registers in an architecture decreases register pressure but increases the cost.<ref>{{cite book |last=Page |first=Daniel |title=A Practical Introduction to Computer Architecture |chapter=11. Compilers |year=2009 |publisher=Springer |isbn=978-1-84882-255-9 |page=464|bibcode=2009pica.book.....P }}</ref>

While embedded instruction sets such as [[ARM Thumb|Thumb]] suffer from extremely high register pressure because they have small register sets, general-purpose RISC ISAs like [[MIPS architecture|MIPS]] and [[DEC Alpha|Alpha]] enjoy low register pressure. CISC ISAs like x86-64 offer low register pressure despite having smaller register sets. This is due to the many addressing modes and optimizations (such as sub-register addressing, memory operands in ALU instructions, absolute addressing, PC-relative addressing, and register-to-register spills) that CISC ISAs offer.<ref>{{cite conference |last1=Venkat |first1=Ashish |last2=Tullsen |first2=Dean M. |title=Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor |year=2014 |conference=41st Annual International Symposium on Computer Architecture |url=http://dl.acm.org/citation.cfm?id=2665692}}</ref>