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→SIMD, SIMT and vector predication: ILLIAC IV had masked Predicated SWAR! only 2 bits (2x32 or 1x64) but still! Tags: Mobile edit Mobile web edit Advanced mobile edit |
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{{Distinguish|branch prediction}}
In [[computer architecture]], '''predication''' is a feature that provides an alternative to [[Conditional (computer programming)|conditional]] transfer of [[control flow|control]], as implemented by conditional [[branch (computer science)|branch]] machine [[instruction (computer science)|instructions]]. Predication works by having conditional (''predicated'') non-branch instructions associated with a ''predicate'', a [[Boolean data type|Boolean value]] used by the instruction to control whether the instruction is allowed to modify the architectural state or not. If the predicate specified in the instruction is true, the instruction modifies the architectural state; otherwise, the architectural state is unchanged. For example, a predicated move instruction (a conditional move) will only modify the destination if the predicate is true. Thus, instead of using a conditional branch to select an instruction or a sequence of instructions to [[Execution (computing)|execute]] based on the predicate that controls whether the branch occurs, the instructions to be executed are associated with that predicate, so that they will be executed, or not executed, based on whether that predicate is true or false.<ref name="rvinyard">{{cite web |author=Rick Vinyard |date=2000-04-26 |title=Predication |url=https://www.cs.nmsu.edu/~rvinyard/itanium/predication.htm |archive-url=https://web.archive.org/web/20150420152310/https://www.cs.nmsu.edu/~rvinyard/itanium/predication.htm |archive-date=20 Apr 2015 |url-status=dead |access-date=2014-04-22 |website=cs.nmsu.edu}}</ref>
[[Vector processors]], some [[SIMD]] ISAs (such as [[AVX2]] and [[AVX-512]]) and [[GPU]]s in general make heavy use of predication, applying one bit of a conditional ''mask vector'' to the corresponding elements in the vector registers being processed, whereas scalar predication in scalar instruction sets only need the one predicate bit. Where predicate masks become particularly powerful in [[vector processing]] is if an ''array'' of [[condition_code_register|condition codes]], one per vector element, may feed back into predicate masks that are then applied to subsequent vector instructions.
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<syntaxhighlight lang="c">
if condition
{
else
{
</syntaxhighlight>
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<syntaxhighlight lang="c">
branch_if_condition_to label1
do_something_else
label1:
do_something
label2:
...
</syntaxhighlight>
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<syntaxhighlight lang="c">
(condition)
(not condition)
</syntaxhighlight>
Besides eliminating branches, less code is needed in total, provided the architecture provides predicated instructions. While this does not guarantee faster execution in general, it will if the <code>
Predication's simplest form is ''partial predication'', where the architecture has ''conditional move'' or ''conditional select'' instructions. Conditional move instructions write the contents of one register over another only if the predicate's value is true, whereas conditional select instructions choose which of two registers has its contents written to a third based on the predicate's value. A more generalized and capable form is ''full predication''. Full predication has a set of predicate registers for storing predicates (which allows multiple nested or sequential branches to be simultaneously eliminated) and most instructions in the architecture have
==Advantages==
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*Predication complicates the hardware by adding levels of [[control unit|logic]] to critical [[datapath|paths]] and potentially degrades clock speed.
*A predicated block includes cycles for all operations, so shorter [[control-flow graph|paths]] may take longer and be penalized.
* An extra register read is required. A non-predicated ADD would read two registers from a register file, where a Predicated ADD would need to also read the predicate register file. This increases Hazards in [[Out-of-order execution]].
*Predication is not usually speculated and causes a longer dependency chain. For ordered data this translates to a performance loss compared to a predictable branch.<ref>{{cite web |last1=Cordes |first1=Peter |title=assembly - How does Out of Order execution work with conditional instructions, Ex: CMOVcc in Intel or ADDNE (Add not equal) in ARM |url=https://stackoverflow.com/a/50960323 |website=Stack Overflow |quote=Unlike with control dependencies (branches), they don't predict or speculate what the flags will be, so a cmovcc instead of a jcc can create a loop-carried dependency chain and end up being worse than a predictable branch. [https://stackoverflow.com/questions/50959808 gcc optimization flag -O3 makes code slower than -O2] is an example of that.}}</ref>
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== SIMD, SIMT and vector predication ==
{{see also|Single instruction, multiple threads}}
Some [[SIMD within a register]] instruction sets, like AVX2, have the ability to use a logical [[Mask (computing)|mask]] to conditionally load/store values to memory, in a parallel form of the conditional move
This form of multi-bit predication is also used in [[vector processors]] at the element level (synonymous with SWAR sub-words):
<syntaxhighlight lang="c">
for each (sub-word i) of SWAR (or Vector) register
(condition-maskbit i) do_something(sub-word i)
(not condition-maskbit i) do_something_else(sub-word i)
</syntaxhighlight>
Masking is an integral part of [[Flynn's taxonomy|Array Processors]] such as the [[ILLIAC IV]]. Array Processors are known today as [[single instruction, multiple threads]] (SIMT), and a predicate bit ''per PE'' used to activate or de-activate each Processing Element. When the PE has no [[SIMD within a register]] instructions, each PE may be individually Predicated:
<syntaxhighlight lang="c">
for each (PE j) // of non-SWAR synchronously-concurrent array
(active-maskbit j) broadcast_scalar_instruction_to(PE j)
</syntaxhighlight>
Modern SIMT [[GPUs]] use (or used, but ILLIAC IV documentation termed it [[ILLIAC IV#Branches|"branching"]]) predication to enable/disable individual Processing Elements ''and'', separately and furthermore, to ''also'' mask-out sub-words within any given PE's SWAR ALU.
<syntaxhighlight lang="c">
for each (PE j) of SIMT synchronously-concurrent array
(active-maskbit j) { // broadcast only to active SWAR PEs
for each (sub-word i) of SWAR register in (PE j)
(condition-maskbit i) do_something(sub-word i)
(not condition-maskbit i) do_something_else(sub-word i)
}
</syntaxhighlight>
All the techniques, advantages and disadvantages of single scalar predication apply just as well to the parallel processing case, where the issues associated with branching are made far more complex.<ref>https://gpgpuarch.org/en/basic/simt/</ref>
==See also==
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