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→Disadvantages: adding extra read hazard disadvantage Tags: Mobile edit Mobile web edit Advanced mobile edit |
→SIMD, SIMT and vector predication: ILLIAC IV had masked Predicated SWAR! only 2 bits (2x32 or 1x64) but still! Tags: Mobile edit Mobile web edit Advanced mobile edit |
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Masking is an integral part of [[Flynn's taxonomy|Array Processors]] such as the [[ILLIAC IV]]. Array Processors are known today as [[single instruction, multiple threads]] (SIMT), and a predicate bit ''per PE'' used to activate or de-activate each Processing Element. When the PE has no [[SIMD within a register]] instructions, each PE may be individually Predicated:
<syntaxhighlight lang="c">
for each (PE j) // of
(active-maskbit j) broadcast_scalar_instruction_to(PE j)
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Modern SIMT [[GPUs]] use (or used, but ILLIAC IV documentation termed it [[ILLIAC IV#Branches|"branching"]]) predication to enable/disable individual Processing Elements ''and'', separately and furthermore, to ''also'' mask-out sub-words within any given PE's SWAR ALU.
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