Put simply: if the Register Condition bit is set, the instruction is executed; if the bit is clear, it is not. With Condition Register's contents being dynamic, predicated instruction execution is likewise dynamic, i.e. (conditionally) determined at runtime.
[[Vector processors]], some [[SIMD]] ISAs (such as [[AVX2]] and [[AVX-512]]]) and [[GPU]]s in general make heavy use of predication, applying one bit of a conditional ''mask Vector'' to the corresponding elements in the Vector registers being processed, whereas scalar predication in scalar instruction sets only need the one predicate bit. Where Predicate Masks become particularly powerful in [[Vector processing]] is if an ''array'' of [[Condition_code_register|Condition Codes]], one per Vector element, may feed back into Predicate Masks that are then applied to subsequent Vector instructions.
