Predication (computer architecture): Difference between revisions

Revision as of 07:13, 27 July 2025

Revision as of 07:21, 27 July 2025

Line 72:

{{see also|Single instruction, multiple threads}}

Some [[SIMD within a register]] instruction sets, like AVX2, have the ability to use a logical [[Mask (computing)|mask]] to conditionally load/store values to memory, in a parallel form of the conditional move,. andThey may also apply individual mask bits to individual arithmetic units executing a parallel operation. One predicate mask bit is available for each sub-word of the SWAR register or each load/store value.

This form of multi-bit predication is also used in [[vector processors]] (at the sub-word, or element level) and was an integral part of [[Flynn's taxonomy|Array Processors]] such as the [[ILLIAC IV]]. Array Processors are known today as [[single instruction, multiple threads]] computing(SIMT). used inModern modernSIMT [[GPUs]], bothuse predication to enable/disable individual Processing Elements ''and'', separately and furtherfurthermore, to ''also'' mask-out sub-words within any given PE's SWAR ALU.

All the techniques, advantages and disadvantages of single scalar predication apply just as well to the parallel processing case.

==See also==