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→SIMD, SIMT and vector predication: bring Flynn taxonomy back in, clarify Tags: Mobile edit Mobile web edit Advanced mobile edit |
→SIMD, SIMT and vector predication: add pseudocode illustrating masking Tags: Mobile edit Mobile web edit Advanced mobile edit |
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Some [[SIMD within a register]] instruction sets, like AVX2, have the ability to use a logical [[Mask (computing)|mask]] to conditionally load/store values to memory, in a parallel form of the conditional move. They may also apply individual mask bits to individual arithmetic units executing a parallel operation. One predicate mask bit is available for each sub-word of the SWAR register or each load/store value.
<syntaxhighlight lang="c">
for each (sub-word i) of SWAR register
(condition-maskbit i) do_something(sub-word i)
(not condition-maskbit i) do_something_else(sub-word i)
</syntaxhighlight>
This form of multi-bit predication is also used in [[vector processors]] (at the sub-word, or element level) and was an integral part of [[Flynn's taxonomy|Array Processors]] such as the [[ILLIAC IV]]. Array Processors are known today as [[single instruction, multiple threads]] (SIMT). Modern SIMT [[GPUs]] use predication to enable/disable individual Processing Elements ''and'', separately and furthermore, to ''also'' mask-out sub-words within any given PE's SWAR ALU.
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