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→SIMD, SIMT and vector predication: add pseudocode illustrating masking Tags: Mobile edit Mobile web edit Advanced mobile edit |
→SIMD, SIMT and vector predication: make pseudocode a little clearer Tags: Mobile edit Mobile web edit Advanced mobile edit |
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This form of multi-bit predication is also used in [[vector processors]] (at the sub-word, or element level) and was an integral part of [[Flynn's taxonomy|Array Processors]] such as the [[ILLIAC IV]]. Array Processors are known today as [[single instruction, multiple threads]] (SIMT).
<syntaxhighlight lang="c"> for each (PE j) // of ILLIAC IV synchronously-concurrent array (active-maskbit j) broadcast_scalar_instruction_to(PE j) </syntaxhighlight> Modern SIMT [[GPUs]] use predication to enable/disable individual Processing Elements ''and'', separately and furthermore, to ''also'' mask-out sub-words within any given PE's SWAR ALU. <syntaxhighlight lang="c">
for each (PE j) of SIMT synchronously-concurrent array
(active-maskbit j) { // broadcast only to active SWAR PEs
for each (sub-word i) of SWAR register in (PE j)
(condition-maskbit i) do_something(sub-word i)
(not condition-maskbit i) do_something_else(sub-word i)
}
</syntaxhighlight>
All the techniques, advantages and disadvantages of single scalar predication apply just as well to the parallel processing case.
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