Predication (computer architecture): Difference between revisions

Revision as of 08:09, 27 July 2025

Revision as of 08:36, 27 July 2025

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Some [[SIMD within a register]] instruction sets, like AVX2, have the ability to use a logical [[Mask (computing)|mask]] to conditionally load/store values to memory, in a parallel form of the conditional move. They may also apply individual mask bits to individual arithmetic units executing a parallel operation. One predicate mask bit is available for each sub-word of the SWAR register or each load/store value.

This form of multi-bit predication is also used in [[vector processors]] at the element level (synonymous with SWAR sub-words):

<syntaxhighlight lang="c">

for each (sub-word i) of SWAR (or Vector) register

(condition-maskbit i) do_something(sub-word i)

(not condition-maskbit i) do_something_else(sub-word i)

</syntaxhighlight>

This form of multi-bit predicationMasking is also used in [[vector processors]] (at the sub-word, or element level) and was an integral part of [[Flynn's taxonomy|Array Processors]] such as the [[ILLIAC IV]]. Array Processors are known today as [[single instruction, multiple threads]] (SIMT)., and a predicate bit used to activate or de-activate each Processing Element:

<syntaxhighlight lang="c">

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</syntaxhighlight>

All the techniques, advantages and disadvantages of single scalar predication apply just as well to the parallel processing case, where the issues associated with branching are made far more complex.

==See also==