Vector processor: Difference between revisions

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IBM 370 Vector facility: explain 370 assembler code
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IBM 370 Vector facility: browser keeps crashing, adding Libre-SOC assembler
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Further, both the Vector-Load and Vector-Store instructions could perform the update of the address registers, saving on explicit instructions to perform address-calculations that ''in effect'' had already been done, behind the scenes, when loading/storing each element of the Vector.
 
The exact same principle is used in [[Libre-SOC]]:<ref>https://libre-soc.org/openpower/sv/cookbook/daxpy_example/</ref>
 
<syntaxhighlight lang=gas>
# r5: n count; r6: x ptr; r7: y ptr; fp1: a
1 mtctr 5 # move n to CTR
2 .L2 setvl MAXVL=32,VL=CTR # actually VL=MIN(MAXVL,CTR)
3 sv.lfdup *32,8(6) # load x into fp32-63, incr x
4 sv.lfd/els *64,8(7) # load y into fp64-95, NO INC
5 sv.fmadd *64,*64,1,*32 # (*y) = (*y) * (*x) + a
6 sv.stfdup *64,8(7) # store at y, post-incr y
7 sv.bc/ctr .L2 # decr CTR by VL, jump !zero
8 blr # return
</syntaxhighlight>
 
=== Vector reduction example ===